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shyvana
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Registered: ‎01-23-2015

Simulation Input Stimulus Control.

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I am working on a project where I have to save 1600bits (32 words) on a bus to Block Ram. This data will be read back in bytes later. Verliog is the language I am designing in. At this point got everything working well with the input [1599:0] with the input as {50{32'hDEADBEEF}}. The data writes to BRAM and is getting read back. 

 

I would like to know if there are any way to generate a concatenation of 32 bit words, that are incremental data.  such as {0x00000001,0x00000002,0x00000003,...}. This is so I can validate the rams contents are being read back in order.

Thanks,

-SHYVANA

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a_chami
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Registered: ‎04-12-2017

In that case, use a counter to write your block RAM.

 

You can write from the counter to a long register, and from the register, once it is full, to the RAM. You will need also to add a MUX to decide if the RAM is written from normal logic or from the initialization logic.

Avi Chami MSc
FPGA Site

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a_chami
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Registered: ‎04-12-2017

You can initialize your Block RAM using a .coe file.

 

https://www.xilinx.com/itp/xilinx10/isehelp/cgn_r_coe_file_syntax.htm

 

The values can be generated in several ways, with the Memory Editor tool, with a Matlab script, with a VHDL testbench...

Avi Chami MSc
FPGA Site
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shyvana
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Registered: ‎01-23-2015
I was hoping to generate the values at the input of my state machine. This is to ensure bits are being written/read from memory correctly.
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a_chami
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Registered: ‎04-12-2017

In that case, use a counter to write your block RAM.

 

You can write from the counter to a long register, and from the register, once it is full, to the RAM. You will need also to add a MUX to decide if the RAM is written from normal logic or from the initialization logic.

Avi Chami MSc
FPGA Site

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shyvana
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Registered: ‎01-23-2015
Yep, thanks very much for your time, that is what I ended up doing. I had a function initialize the registers with a for-loop. I was hoping there was a more elegant way than this possibly using the concatenation operators.
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a_chami
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Registered: ‎04-12-2017

Maybe there is, and I will be happy to know if there is one.

 

However, not always the "ellegant" or "compact" way of coding is the best. The code you wrote, if it is clear enough, it is better even if it is not "ellegant", since when you maintain your code one year from now it will be (probably) much easier to mantain the code if it is clear and simple rather than ellegant and obscure.

 

Of course, if there is an ellegant AND clear way to do it, I will also be glad to know. Until then, your straight forward solution is just fine.

Avi Chami MSc
FPGA Site
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