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Highlighted
1,287 Views
Registered: ‎09-28-2019

Simulation about 30MHz to 1Hz clock divider

Hi everyone,

I have a question about simulation (30MHz to 1Hz clock divider).

I used a VHDL code and Modelsim Tool for clock divider.
Then, I want to get a simulation result about 50% duty cycle of 1Hz clock.
I got a result for my simulation about 0.499s rising clock and 0.98 falling clock.
How can I get a accurate simulation result of 50% duty cycle 1Hz clock?

 

Thanks for your advices.

 

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5 Replies
Highlighted
Moderator
Moderator
1,253 Views
Registered: ‎05-31-2017

@modelsim_xilinx ,

There should be some issues with your created frequency divider HDL code. Please check the functionality of your code whether it actually divides the clock to 1Hz from 30 MHz.

I hope you are using the method of scaling factor for the clock divider, if not you can try using the scaling factor and see if it helps as the frequency divider can easily be constructed from a scaling factor and a counter.

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Teacher
Teacher
1,234 Views
Registered: ‎07-09-2009

sharing your code would help us

have a look here
its the standard way of generating a clock
https://allaboutfpga.com/vhdl-testbench-tutorial/
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Highlighted
1,193 Views
Registered: ‎09-28-2019

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity Clock_Divider is
port ( clk,reset: in std_logic;
clk_out: out std_logic);
end Clock_Divider;
 
architecture bhv of Clock_Divider is
 
signal count: integer:=0;
signal tmp : std_logic := '0';
 
begin
 
process(clk)
begin
if(clk'event and clk='1') then
  count <=count+1;
  if (count = 15015015) then
    tmp <= NOT tmp;
    count <= 1;
  end if;
end if;
clk_out <= tmp;
end process;
 
end bhv;
-----------------------------------------------------------------------------
*** testbench ***
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY Tb_clock_divider IS
END Tb_clock_divider;
 
ARCHITECTURE behavior OF Tb_clock_divider IS
 
-- Component Declaration for the Unit Under Test (UUT)
 
COMPONENT Clock_Divider
PORT(
clk : IN std_logic;
reset : IN std_logic;
clk_out : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
 
--Outputs
signal clk_out: std_logic;
 
-- Clock period definitions
constant clk_period : real := 30000000;
constant clk_1 : time := 1/clk_period;
constant rising_time : time := clk_1/2;
constant falling_time : time := clk_1 - rising_time;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: Clock_Divider PORT MAP (
clk => clk,
reset => reset,
clk_out=> clk_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for falling_time;
clk <= '1';
wait for rising_time;
end process;

END;

Thanks for your reply.

Here is my VHDL code and testbench.

However, I couldn`t get a accurate 50% duty cycle of 1Hz.

How can I do this?

0 Kudos
Highlighted
1,191 Views
Registered: ‎09-28-2019

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity Clock_Divider is
port ( clk,reset: in std_logic;
clk_out: out std_logic);
end Clock_Divider;
 
architecture bhv of Clock_Divider is
 
signal count: integer:=0;
signal tmp : std_logic := '0';
 
begin
 
process(clk)
begin
if(clk'event and clk='1') then
  count <=count+1;
  if (count = 15015015) then
    tmp <= NOT tmp;
    count <= 1;
  end if;
end if;
clk_out <= tmp;
end process;
 
end bhv;
-----------------------------------------------------------------------------
*** testbench ***
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY Tb_clock_divider IS
END Tb_clock_divider;
 
ARCHITECTURE behavior OF Tb_clock_divider IS
 
-- Component Declaration for the Unit Under Test (UUT)
 
COMPONENT Clock_Divider
PORT(
clk : IN std_logic;
reset : IN std_logic;
clk_out : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
 
--Outputs
signal clk_out: std_logic;
 
-- Clock period definitions
constant clk_period : real := 30000000;
constant clk_1 : time := 1/clk_period;
constant rising_time : time := clk_1/2;
constant falling_time : time := clk_1 - rising_time;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: Clock_Divider PORT MAP (
clk => clk,
reset => reset,
clk_out=> clk_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for falling_time;
clk <= '1';
wait for rising_time;
end process;

END;

Thanks for your reply.

Here is my VHDL code and testbench.

However, I couldn`t get a accurate 50% duty cycle of 1Hz.

How can I do this?

0 Kudos
Highlighted
Teacher
Teacher
1,171 Views
Registered: ‎07-09-2009

your a test bench
there is no rising / falling edge, its a single delta

the code I posted has how to do this

You also need to look at a more modern text book,
try this as a statr
http://freerangefactory.org/

BTW: if(clk'event and clk='1') then has not been used for 20 plus years



<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>