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Explorer
Explorer
10,219 Views
Registered: ‎11-25-2015

Simulation and Verification Resources

Simulation and Verification forum is the open platform to discuss about simulation and verification tools and flows, including XSIM and ISE Simulator™, 3rd party simulators.

 If you can’t find your answer in the below existing documentation, please always feel free to post your question on this Forum’s page.

 

User Guides: Xilinx technical documents intended for better performance and understanding.

Vivado:

UG 900: Vivado Design Suite User Guide Logic Simulation

UG 937: Vivado Design Suite Tutorial Logic Simulation

ISE:

UG 626: Synthesis and Simulation Design Guide

UG 682: ISim In-Depth Tutorial

 

Video Tutorials: Xilinx graphical demonstration for ease of use approach specific to the application.

Simulation using Vivado

Simulation using Cadence IES

Simulation using Synopsys VCS

Simulation using Mentor Graphics Questa

 

Simulator product brief:

Vivado

ISE

 

Answer Records: Xilinx answer records are public accessible documents specific to use cases or issues. You can search this AR’s on Xilinx website.

Simulation Solution Center

Vivado 2015.x known issues

Vivado 2016.x known issues

 

 

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10 Replies
Visitor omahesh
Visitor
10,084 Views
Registered: ‎02-01-2017

Re: Simulation and Verification Resources

Hi Sravanthi,

 

       One quick question: Do you have any suggestion or example for Compiling and simulating .XCIX file with Cadence tool in the

LINUX environment.?

       If so, can you share some suggestions?

 

Regards,

mahesh

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Moderator
Moderator
9,528 Views
Registered: ‎04-24-2013

Re: Simulation and Verification Resources

Hi Mahesh,

 

If you are still looking for information on running simulations in Cadence then you can check which version of Cadence is compatible with each version of Vivado in User Guide 973. If you use incompatible versions then you will get compile errors

 

You can compile the libraries either via the GUI with Tools, Compile Simulation Libraries or via the tcl console

 

compile_simlib -language all -dir {/path_to_compile_to/compile_simlib} -simulator ies -simulator_exec_path {/tools/gensys/questa/10.5c/bin} -library all -family  all

 

If you wish to generate the scripts to run the simulation then you can use the export_simulation tcl command

 

The following command generates a script file "accum_0_sim_ies.sh" for the "accum_0" IP in the
specified output directory for the "IES" simulator:

 

export_simulation -of_objects [get_files accum_0.xci] -directory "test_sim" -simulator ies -lib_map_path "/path_to_compile_to/compile_simlib"

 

Regards
Aidan

 

 

 

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Observer shivanagis
Observer
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Registered: ‎09-28-2016

Re: Simulation and Verification Resources

@svanapar@amaccre I am using Vivado 2014.4 and Questasim 10.4b version tools. I have a design which has Xilinx IP cores. Now I want to do simulate and Verification in Questasim for the same design. Please suggest me that how can a achieve this.

 

Thanks in advance

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Moderator
Moderator
8,549 Views
Registered: ‎04-24-2013

Re: Simulation and Verification Resources

Hi @shivanagis

 

To compile the Xilinx IP libraries for QuestaSim 10.4b there are two options, you can either do so from the GUI or from the command line.

 

In the GUI you can choose Tools, Compile Simulation Libraries.

 

In here select QuestaSim as the simulator.

Enter the values for where QuestaSim is installed on your system and where you want to store the simulation libraries.

 

Screenshot.png

 

You can do the same thing in the tcl console:

 

compile_simlib -language all -dir {/home/amaccre/compile_simlib/10_4b} -simulator questa -simulator_exec_path {/tools/gensys/questa/10.4b/bin} -library all -family  all

 

When this is finished running you should see no errors.

 

User Guide 900 has a chapter on compiling the simulation libraries and on simulating the design with QuestaSim.

I've attached the pdf for 2014.4

 

Let me know if this helps.

Best Regards
Aidan

 

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Observer shivanagis
Observer
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Registered: ‎09-28-2016

Re: Simulation and Verification Resources

Hello @amaccre I followed the procedure as you suggest but its throwing some errors.

 

Please find the attachment.

 

Thanks in advance.

 

compile simulation library.png
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Moderator
Moderator
8,506 Views
Registered: ‎09-15-2016

Re: Simulation and Verification Resources

Hi @shivanagis,

 

Can you please try and check the below command to compile the simulation libraries. Also, looks like you have mentioned same path for compiled library location and simulator executable path. 

 

The Compiled library location specifies the directory path for saving the compiled library results. By default,  the libraries are saved in the <project>/<project>.cache/compile_simlib directory in Project mode. Can you please try using a specified path to the directory to save the libraries.

 

The Simulator executable path specifies the directory to locate the simulator executable. Hence, please specify the executable path and then run compile. 

 

Mention the simulator settings as below and if you still face any errors then can you please share the compile_simlib.log located in the working directory. Type "pwd" in Tcl console to view the location.

 

compile_simlib -force -language all -dir {C:/Users/bandi/questa} -simulator questa -simulator_exec_path {/tools/gensys/questa/10.4b/bin} -32bit  -verbose  -library all -family  all

 

Thanks & Regards,

Sravanthi B

 

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questa.JPG

Thanks & Regards,
Sravanthi B
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Moderator
Moderator
8,496 Views
Registered: ‎04-24-2013

Re: Simulation and Verification Resources

Hi @shivanagis,

 

I only have a Linux version of the tools so my paths look different but the procedure is exactly the same on Windows.

 

In the screen shot that you provided you have both the Compile Library Location and the Simulator executable path pointing to the same windows folder. This is incorrect.

 

The Simulator executable path should point to where the .exe file for Questa is, in this case it looks correct (but I can't check for sure).

 

The Compile Library Location is incorrect. This should be set to where you want to save the files being generated. You can create a folder somewhere on your machine and point to this location. I have a folder called compile_simlib and within this I create sub folders for the version of the tools. This allows me to have libraries on hand for multiple versions of the Simulator.

 

For example you might have a folder called c:\compile_simlib\10_4b and point your Compile Library Location to this location.

 

If you are using a 32bit verson of the tools then it is correct to click the Compile 32-bit libraries.

 

Pages 129 -149 of User Guide 900 attached to the last post has step by step details on how to compile and run a simulation using Questa.

 

Let me know if this helps.

Best Regards
Aidan

 

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Observer shivanagis
Observer
8,481 Views
Registered: ‎09-28-2016

Re: Simulation and Verification Resources

@amaccre @bandi Thank you :).

 

Its done with compile simulation libraries.

 

Best regards

Shashi

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Moderator
Moderator
8,255 Views
Registered: ‎09-15-2016

Re: Simulation and Verification Resources

Hi @shivanagis,

 

Glad to know that you were able to compile the simulation libraries.

 

Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
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Visitor coldfiremc
Visitor
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Registered: ‎09-23-2018

Re: Simulation and Verification Resources

Hi, I'm trying to to some FSM coverage with Vivado 2018.2 and ModelSim. For that, I need to add some flags. However, despite I add them, the script generator appears to ignore them.
Specifically I'm adding flags to vopt 

modelsim.elaborate.vopt.more_options*+acc +cover


but the generated script is just

######################################################################
#
# File name : top_clock_simulate.do
# Created on: Sat Oct 20 16:20:59 -0300 2018
#
# Auto generated by Vivado for 'behavioral' simulation
#
######################################################################
vsim -debugDB -coverage -L xil_defaultlib -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.top_clock

do {top_clock_wave.do}

view wave
view structure
view signals

log -r /*

do {top_clock.udo}

run 1000ns

Can you help me to debug this? is this a bug?

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