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Registered: ‎08-04-2018

Simulation- data type



Here is my testbench


library IEEE;
use ieee.numeric_std.all;
use std.textio.all;
entity test_design_1 is end test_design_1; architecture TB of test_design_1 is component design_1 is port ( dclk_in : in STD_LOGIC; eoc_out : out STD_LOGIC; vn_in : in STD_LOGIC; vp_in : in STD_LOGIC ); end component design_1; signal dclk_in : STD_LOGIC; signal eoc_out : STD_LOGIC; signal vn_in : STD_LOGIC; signal vp_in : STD_LOGIC; begin DUT: component design_1 port map ( dclk_in => dclk_in, eoc_out => eoc_out, vn_in => vn_in, vp_in => vp_in ); process variable value_SPACE : character; variable read_col_from_input_buf : line; variable value_TIME, value_VP, value_VN : real; file input_buf : text; begin file_open(input_buf, "design.txt", read_mode); while not endfile(input_buf) loop readline(input_buf, read_col_from_input_buf); read(read_col_from_input_buf, value_TIME); read(read_col_from_input_buf, value_SPACE); -- read in the space character read(read_col_from_input_buf, value_VP); read(read_col_from_input_buf, value_SPACE); -- read in the space character read(read_col_from_input_buf, value_VN);

--how to convert the values here? from real to std_logic
dclk_in <= (value_TIME); vn_in <= (value_VN); vp_in <= (value_VP); end loop; end process; end TB;


mv values are 






Here is my design block


I am trying to use .txt for simulation here.



here is my sources 





I am trying to assign the value from the file to pins vn_in, vp_in, and dclk and see the eoc as output.


But how do i convert the type here? In the process i want to assign the value to the ports but I am getting confused with the type, because the data are in real type in the file while the actual inpt expected at the port is type 0 or 1.


Help me, thank you. 


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1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎09-24-2017

Hi @benaka,

For your another post, I previously said that you need to feed data to input pins in testbench. However it is not the case for this analogy signal pin. Sorry, I don't consider that this is a special case.

For this case, the input pin of vp_in and vn_in is for analog signals in hardware. And in testbench, analogy signals can't be fed to vp_in directly. In port declaration of xadc, the type of vp_in is 'std_logic', it can't be fed by analogy signal.

For simulation of XADC, analog signals are read from a file by the simulation model. The SIM_MONITOR_FILE attribute used in the XADC instantiation points the model to the location of this file known as the Analog Stimulus file. You can find the description of this situation in ug480.

Best Regards,





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