Simulation error: [VRFC 10-2063] Module not found while processing module instance

[sam025023]

Vivado 2014.1 +win7 are used in my case. 

In the simulation top verilog file, an AXI BRAM Controller 4.0 has been created and instantiated. This IP only used in simulation. 

When I tried to run the simulation, an error occurs:

[VRFC 10-2063] Module <axi_bram_ctrl_1> not found while processing module instance <axi_bram_controller> ["C:/**/TB_*e.v":333]

I googled and found there some similar cases like this. In Out of Context Setting, checkpoints file .dcp for this IP is disanbled. Then tried to run simulation again. There is still the same error.

Please help.

Appreciate it.

Sam

[vemulad]

Hi Sam,

Once you run behavioral simulation, you can check .sim --> sim_1 --> behav folder (in project directory) for the .prj file.

Check this prj file to see if the files of BRAM controller are present or not.

There is no need of disabling "out of context" setting for the IP. The issue which you read about is in vivado 2013.2 which is fixed in 2013.3. As you are using vivado 2014.1 there is no need of disabling this.

Thanks,

Deepika.

[debrajr]

Something else to try. Right click on the IP and select Reset Output Products followed by Generate Output Products and then try simulation.

[neilveira]

Hello, I'm having the exact same problem in Vivado 2016.2. I have 2 modules (one is an IP and one is my own module) which are being detected correctly by synthesis and elaboration but I get this error during post-synthesis functional simulation. I've tried regenerating the IP and adding the files to the simulation manually but nothing works.

Any suggestions? Thanks. 

[neilveira]

Well I managed to get around the error now. I'm not completely sure how but I think it may have been fixed by setting -flatten_hierarchy to "none" in the synthesis settings. 

[neilveira]

Actually I hit the error again even with -flatten_hierarchy "none". Looks like it can be fixed by simply closing vivado and then opening the project again. 

[rikraf]

I had this problem, too, in Viv2016.2.  I have a project I've been working with for many months, copied it to a new location to create a new version, and suddenly the simulator could not find many modules, both IP and Verilog modules that I had written (even though all of the modules showed up in the simulation hierarchy).  I exited Vivado and got back in, no help.  I finally cleared it up by doing the following:

In the simulation hierarchy, I selected one (out of 20) of the modules that were not found.  I unchecked "Used In Simulation" in the properties for this module.  Then I checked it again.  Then ran simulation, and all was well.

Rick

[olupj]

Just found this error in vivado 2019.2 Ubuntu 18.04.

Here's the workaround that seems to allowed my simulation of XCI files within a systemverilog design.

I closed, reopened the tool - didn't affect that error message.

I changed project settings from Mixed to Verilog. Then closed, reopened the tool. Still an issue. Then I changed the settings from Verilog to mixed. This *may* have been what enabled simulation to work correctly.

Xilinx: it shouldn't be this hard nor random. This is a specific simulation project that was TCL driven in vivado project mode.

Here's the errors during xelab, FYI, before the intractable problem and subsequent fix...

ERROR: [VRFC 10-2063] Module <lpf_nn_system> not found while processing module instance <lpf_i> [tt_channelizer.sv:239]
ERROR: [VRFC 10-2063] Module <hb_nn_2> not found while processing module instance <hb1_filt> [tt_channelizer.sv:298]
ERROR: [VRFC 10-2063] Module <hb_nn_3> not found while processing module instance <hb2_filt> [tt_channelizer.sv:347]
ERROR: [VRFC 10-2063] Module <tt2_mac> not found while processing module instance <tt2_mac_isnt> [tt_Nchan.sv:270]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

- Jerry

[olupj]

Hi,

Had this exact problem again. The "solution" is not repeatable.

Going to create a new simulation project. Thankfully scripts save me from Vivado's shortcomings.

[mxdsgnl]

@avrumwYour posts are always critically valuable to solve these sorts of issues.  See: https://forums.xilinx.com/t5/Synthesis/system-Verilog-pkg-import/td-p/926623

This feels like a compilation order issue as well.  I have had this same problem where out of nowhere a perfectly functioning simulation just quits and the elaborate.log has the cryptic error.  The listed files are obviously in scope and available as they are visible in the tree view.

Do you know where the tool is getting mixed up?

Thanks,

Nick

[mxdsgnl]

I was able to turn this problem on and off.  The compilation order and build script that we use to export and rebuild packaged IP for a consuming project required an update.  Following the suggestion specified in https://forums.xilinx.com/t5/Synthesis/system-Verilog-pkg-import/td-p/926623 allowed Vivado to synthesize the packaged IP, but not simulate it. I ended up removing everything from @avrumw 's post

Two items required a minor update.

1.  In IP packager of the source CIP:

• Make sure that any systemverilog packages are listed above any module that imports them In the IP Packager "Files" tab.
• Make sure your export script preserves this order (Mine was alphabetical and that was one problem)

No more problems.  Can't explain why it would work sometimes and not others.  However, with this update, it workds 100%.

Thanks,

Nick