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Observer rickardaf
Observer
12,567 Views
Registered: ‎04-10-2014

Simulation error in Vivado 2013.4 [Simtcl 6-30]

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Hello,

 

I'm trying to run simulation but getting error:

ERROR: [Simtcl 6-30] Unable to locate simulation image at 'xsim.dir/tb_time_synth/xsimk.exe'
[Vivado 12-2332] Received fatal error while launching XSIM application!

 

I've tried

Run behavioral simulation
Run post-synthesis functional simulation
Run post-synthesis timing simulation
Run post-implementation functional simulation
Run post-implementation timing simulation

 

and they're all giving me the same error.

 

I'm running Windows 7 pro SP1 64 bit and using Vivado webpack 2013.4.

 

I've read other forum-threads but no success.

 

I've tried:

running Vivado in 32 bit mode => same error

 

recreating the project and add files and testbench => same error

 

running batch mode => same error

 

reinstalled Vivado => no difference

 

running simulation in TCL mode => same error

 

loading example project (Zynq system) and run simulation on it => same error

 

one thread mentions the program "dependency walker" so I tried it on xsim.exe in both win32.o and win64.o folder,

they gives the same result

LIBBOOST_FILESYSTEM.DLL     Error opening file. Can't find file (2)
LIBBOOST_PROGRAM_OPTIONS.DLL    Error opening file. Can't find file (2)
LIBBOOST_SIGNALS.DLL    Error opening file. Can't find file (2)
LIBRDI_COMMON.DLL    Error opening file. Can't find file (2)
LIBRDI_COMMONMAIN.DLL    Error opening file. Can't find file (2)
SHSMP.DLL    Error opening file. Can't find file (2)
STLPORT.5.2.DLL    Error opening file. Can't find file (2)

 

can somebody help me with this?

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1 Solution

Accepted Solutions
Contributor
Contributor
17,851 Views
Registered: ‎02-20-2014

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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i think it's the problem with the testbench code, especially when some signals in use is without any/correct defination, such as wire or reg signals...i came across with the same problem, though the thread won't report the missing defination as errors and go through, but later the information such as [Simtcl 6-30 ...] prompts out. i checked the test bench code accroding to the messages/log, and added the defination of some signals, then"Running xelab.." can start out to run.FYI.
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10 Replies
Xilinx Employee
Xilinx Employee
12,563 Views
Registered: ‎04-16-2012

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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Hi,

 

What OS are you using?

Also this thread may help you: http://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-2013-4-Simulation-Problem-in-Windows-8/td-p/397171

 

Thanks

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Observer rickardaf
Observer
12,558 Views
Registered: ‎04-10-2014

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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I'm running Windows 7 pro SP1 64 bit.

I've previously tried most of the things in that thread but with no success.
I haven't tried re-adding top level testbench before but I tried it now and unfortunately didn't work.
I've checked and all the files I've created are present.

 

the attached file in the thread from roshansilwal contains the same errors as mine for win64.o/xsim.exe but I get the same errors for win32.0/xsim.exe

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Xilinx Employee
Xilinx Employee
12,548 Views
Registered: ‎07-16-2008

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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Is the issue project specific? Does the error occur if you try an example design?

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Observer rickardaf
Observer
12,535 Views
Registered: ‎04-10-2014

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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It isn't project specific

I've tried loading example project (named "Zynq system") and run simulation on it and I get the same error
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Observer rickardaf
Observer
12,507 Views
Registered: ‎04-10-2014

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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before anybody asks,

 

When I downloaded Vivado I calculated md5 checksum and confirmed that it was correct.

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Observer rickardaf
Observer
12,071 Views
Registered: ‎04-10-2014

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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Some update from my part that might help some support tech solving my problem.

 

I tried removing the testbench file and then put the wrapper as top for the simulation and then it works without error.

I tried it on both my project and the example project (in the example I removed "tb.v" and put "zynq_1_wrapper.vhd" as top) and none of them gives any error.

 

the only problem now is: how can I simulate signals without at testbench???

 

why do I get this error as soon as a testbench is present?

ERROR: [Simtcl 6-30] Unable to locate simulation image at 'xsim.dir/tb_time_synth/xsimk.exe'
[Vivado 12-2332] Received fatal error while launching XSIM application!

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Moderator
Moderator
11,742 Views
Registered: ‎04-17-2011

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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You can force signals without a testbench to your UUT.

Refer page 86:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug900-vivado-logic-simulation.pdf 

Regards,
Debraj
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Xilinx Employee
Xilinx Employee
11,710 Views
Registered: ‎04-16-2012

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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Hi,

 

You can give a try by running simulation in command line mode and invoking the snapshot in GUI.

You can find the steps in UG900. link given in the previous post.

 

Thanks

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Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.
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Contributor
Contributor
17,852 Views
Registered: ‎02-20-2014

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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i think it's the problem with the testbench code, especially when some signals in use is without any/correct defination, such as wire or reg signals...i came across with the same problem, though the thread won't report the missing defination as errors and go through, but later the information such as [Simtcl 6-30 ...] prompts out. i checked the test bench code accroding to the messages/log, and added the defination of some signals, then"Running xelab.." can start out to run.FYI.
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Observer rickardaf
Observer
5,410 Views
Registered: ‎04-10-2014

Re: Simulation error in Vivado 2013.4 [Simtcl 6-30]

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First of all, I'm using VHDL so I don't use 'wire' or 'reg' but I understand what you mean.

 

I have no idea why this should work when errors should reportable as error (at least that's what I think). But I've gone through my testbench and fixed all the warnings (had no error) and now the simulation starts.

 

I didn't think that could be the problem when even the example project got the [Simtcl 6-30 ...] error. I looked through the example project's testbench and it has some warnings (no errors). When I solved them its testproject works as well.

 

Strange that the code works on hardware but not in simulation...

 

Thank you everybody for your help.

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