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Visitor
Visitor
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Registered: ‎10-11-2018

Simulation error in project with two Zynq processors

Hi everyone! We're currently working with a design which contains a Zynq processor, and we want to create a Vivado testbench which consists of two of these designs back to back. However, when we try to run simulation, we're getting the error at the bottom of the post. We've tried in Vivado 2018.1 and 2018.3 on Windows 10. 

I've managed to recreate the issue by creating a new project with a block design containing just two zynq processors (without the rest of our components). We created a wrapper for this block design and then instantiated it in a simple testbench which simply tries to read from a certain address. We saw the same [XSIM 43-3294]  EXCEPTION_ACCESS_VIOLATION error when using the following command to read from one of the processors, but when we comment out the read command, the simulation launches correctly. Does anyone know what we're doing wrong? Is it possible to simulate two zynq processors in the one design? Is there a particular part or board that we need to be using? Thanks!

Read command causing error:

`zynq_proc.read_data(32'h1000_0000,4 ,reg_data,response);

 

Error:

ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
Printing stacktrace...

[0] (KiUserExceptionDispatcher+0x2e) [0x7ffd315bfe3e]
[1] (ISIMC::Options::parseVlogcompCommandLine+0x41096) [0x7ff628908ce6]
[2] (ISIMC::Options::parseVlogcompCommandLine+0xb02e9) [0x7ff628977f39]
[3] (ISIMC::Options::parseVlogcompCommandLine+0xb03cb) [0x7ff62897801b]
[4] (ISIMC::Options::parseVlogcompCommandLine+0xb03cb) [0x7ff62897801b]
[5] (ISIMC::Options::parseVlogcompCommandLine+0xb03cb) [0x7ff62897801b]
[6] (ISIMC::Options::parseVlogcompCommandLine+0xb03cb) [0x7ff62897801b]
[7] (ISIMC::Options::parseVlogcompCommandLine+0xb03cb) [0x7ff62897801b]
[8] (ISIMC::Options::parseVlogcompCommandLine+0xb03cb) [0x7ff62897801b]
[9] (ISIMC::Options::parseVlogcompCommandLine+0xb03cb) [0x7ff62897801b]
[10] (ISIMC::Options::parseVlogcompCommandLine+0xb03cb) [0x7ff62897801b]
[11] (ISIMC::Options::parseVlogcompCommandLine+0xb3231) [0x7ff62897ae81]
[12] (ISIMC::VhdlCompiler::saveParserDump+0x931b8) [0x7ff6288b19f8]
[13]  [0x7ff628625ef4]
[14]  [0x7ff628629af2]
[15]  [0x7ff62862838a]
[16] (ISIMC::Options::parseVlogcompCommandLine+0xac4459) [0x7ff62938c0a9]
[17] (BaseThreadInitThunk+0x14) [0x7ffd2fdd7bd4]

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Moderator
Moderator
103 Views
Registered: ‎09-15-2016

Hi @gavinheaney ,

Can you please share the archived project or the test case to check this issue at our end.

Thanks & Regards,
Sravanthi B
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Visitor
Visitor
84 Views
Registered: ‎10-11-2018

Hi @bandi 

I have attached a copy of the project. It was created with Vivado 2018.1. 

Thanks,

Gavin

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