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trup_tea
Visitor
Visitor
527 Views
Registered: ‎07-04-2020

Simulation error - mixed language or library compilation error?

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Hey!

I wanted to simply debug a VHDL file (let's name it xyz.vhd) using simulation, but as soon as I simulate it, I get this error:

Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance xyz.IBUFG_inst.B1 is set to . Legal values for this attribute are TRUE or FALSE.

trup_tea_0-1611029238620.png

But IBUF_LOW_PWR is set to "FALSE" in the instantiation of the component IBUF in the xyz.vhd file.

I found a few queries similar to this on this forum, but I did not quite understand how to solve this issue. I found that it might be a compilation order problem during the simulation. Hence I went and checked the "compile order" tab in the "Sources" window. But the order there seemed fine, i.e. the ibuf.v file was the first file in the order. Kindly correct me if I am wrong.

Would appreciate any insights on this. Thank you very much in advance

Just for your information, I use Vivado 2018.

 

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trup_tea
Visitor
Visitor
369 Views
Registered: ‎07-04-2020

Hello! I found that the solution for this error was rather simple. I just added the following library declarations to the top module vhdl file:

library UNISIM;
use UNISIM.Vcomponents.all;
library UNIMACRO;
use UNIMACRO.Vcomponents.all;

 

I stopped getting that error. Thank you for your time and help!

View solution in original post

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graces
Moderator
Moderator
515 Views
Registered: ‎07-16-2008

Is your design mixed language? The attribute type could be different between VHDL and Verilog unisim models, i.e. bool vs. string.

How did you load the libraries in simulation commands?

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trup_tea
Visitor
Visitor
471 Views
Registered: ‎07-04-2020

Yes, my design is mixed language, and the simulator language is set to "Mixed" in the simulation settings.

It might be helpful to know that I use Windows10. I am new to this so I'm not sure if this answers your question "How did you load the libraries in simulation commands?"

compile_simlib -simulator_exec_path {C:/Modeltech_pe_edu_10.4a/win32pe_edu} -family all -language all -library all -dir {project path/project_folder.cache/compile_simlib/modelsim}

Found this command in the "Compile Simulation Libraries". Hope this answers your question

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trup_tea
Visitor
Visitor
449 Views
Registered: ‎07-04-2020

I went through the other threads with similar problems and I referred to the following link as well:

https://www.xilinx.com/support/answers/47724.html

I just do not understand where I can find the simulation script in Vivado and how I can make the change of placing unisims_ver prior to unisim.

Thanks in advance!

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miti
Xilinx Employee
Xilinx Employee
430 Views
Registered: ‎06-10-2020

The simulation scripts will get generated at area <project_directory>/<project_name>.sim/sim_1/behav/xsim.

These files will be present : "compile.sh", "elaborate.sh" and "simulate.sh". You can change these files as per your need.

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trup_tea
Visitor
Visitor
375 Views
Registered: ‎07-04-2020

Thank you for your reply. I found text files named simulate, compile and elaborate in <project_directory>/<project_name>.sim/sim_1/behav/xsim. 

Among these files, the "elaborate" file had a line :

--debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot <design_name>_behav xil_defaultlib.<design_name> xil_defaultlib.glbl -log elaborate.log


I modified that part of the line by adding -L unisim -L unimacro to it. But I realised that changing that file does nothing, as it is generated as a result of internal library compilation settings. The file kept changing back to how it was after every attempted simulation. Could you please help me with this?

Thanks in advance!

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trup_tea
Visitor
Visitor
370 Views
Registered: ‎07-04-2020

Hello! I found that the solution for this error was rather simple. I just added the following library declarations to the top module vhdl file:

library UNISIM;
use UNISIM.Vcomponents.all;
library UNIMACRO;
use UNIMACRO.Vcomponents.all;

 

I stopped getting that error. Thank you for your time and help!

View solution in original post

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