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Adventurer
Adventurer
11,804 Views
Registered: ‎03-05-2008

Simulation error on example design for AXI Data Width Converter IP

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Hi all,

 

I'm not sure if this is the correct place to report this ...

 

I'm getting a simulation tool error (ERROR: [XSIM 43-3225]) on an example design for AXI Data Width Converter IP. Strangely enough, an example design for AXI Data FIFO IP simulates without problem. I can't tell why one works and the other doesn't. Anyhow ... here's the log with the error. If anyone can shed light on this I'd be very grateful.
PaulD   

 

Vivado Simulator 2015.1
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.1/bin/unwrapped/win64.o/xelab.exe -wto b7aa771abeec4f278f44a2c31c666ef7 --debug typical --relax --mt 2 --include ../../../axis_dwidth_converter_0_example.srcs/sources_1/ip/axis_dwidth_converter_0/axis_infrastructure_v1_1/hdl/verilog -L lib_cdc_v1_0 -L proc_sys_reset_v5_0 -L xil_defaultlib -L axis_infrastructure_v1_1 -L axis_register_slice_v1_1 -L axis_dwidth_converter_v1_1 -L unisims_ver -L unimacro_ver -L secureip --snapshot exdes_tb_behav xil_defaultlib.exdes_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
ERROR: [XSIM 43-3225] Cannot find design unit xil_defaultlib.exdes_tb in library work located at xsim.dir/work.

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Xilinx Employee
Xilinx Employee
18,885 Views
Registered: ‎02-14-2014

Re: Simulation error on example design for AXI Data Width Converter IP

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Hello @prdorrell,

 

I can see two files in below folder <project_directory>/axi_dwidth_converter_0_example/axi_dwidth_converter_0_example.srcs/sources_1/ip/axi_dwidth_converter_0/axi_register_slice_v2_1/hdl/verilog/

 

The files are 

 

axi_register_slice_v2_1_axi_register_slice.v

axi_register_slice_v2_1_axic_register_slice.v

 

and when I just changed the path of header file in axi_register_slice_v2_1_axi_register_slice.v at line #211, simulation worked for me.

 

Anyways we can conclude that finding the path of header file was the issue. Once you provide absolute path, the simulator is able to pick it and complete the simulation.

 

Currently you can proceed with this workaround. As I mentioned, CR is filed for this issue and appropriate enhancements will be made in future release.

Regards,
Ashish
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Xilinx Employee
Xilinx Employee
11,798 Views
Registered: ‎02-14-2014

Re: Simulation error on example design for AXI Data Width Converter IP

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Hello @prdorrell,

 

Yes, I am able to reproduce this issue with Vivado 2015.1 XSIM simulator. I will investigate this problem and update the thread further.

 

One more observation here is the problem seems to be OS specific. I am able to simulate example design successfully on linux OS. Problem is with Windows-7 64 bit. 

 

 

Regards,
Ashish
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Moderator
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Registered: ‎01-16-2013

Re: Simulation error on example design for AXI Data Width Converter IP

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Hello @prdorrell,

 

Can you attach the xci file to the post? I tried it with Vivado 2015.1 on windows 64 bit and with default values on axi datawidth converter everthing worked fine.

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Adventurer
Adventurer
11,771 Views
Registered: ‎03-05-2008

Re: Simulation error on example design for AXI Data Width Converter IP

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Hi Syed and Ashishd,

 

Thanks for your interest in my problem. I'm attaching the xci file

 

Regards

PaulD

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Adventurer
Adventurer
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Registered: ‎03-05-2008

Re: Simulation error on example design for AXI Data Width Converter IP

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Trying again to add an attachment ...

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Adventurer
Adventurer
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Registered: ‎03-05-2008

Re: Simulation error on example design for AXI Data Width Converter IP

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Trying again to attach file using Chrome browser instead on Internet Explorer ...

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Adventurer
Adventurer
11,760 Views
Registered: ‎03-05-2008

Re: Simulation error on example design for AXI Data Width Converter IP

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OK, so there is a problem using Internet Explorer to send attachments ... but Chrome works!

My customization of axis_dwidth_converter is very simple:
108, 4 No, No, Yes, 0, 0, 0, No
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Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Re: Simulation error on example design for AXI Data Width Converter IP

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Hello @prdorrell,

 

To workaround this issue, open axi_register_slice_v2_1_axi_register_slice.v file in any text editor outside vivado and save the file after adding complete path of axi_infrastructure_v1_1_header.vh header at line #211. Now run Behavioral Simulation.

 

I have filed CR to include this information about error message in the generated log files.

Regards,
Ashish
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Adventurer
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Registered: ‎03-05-2008

Re: Simulation error on example design for AXI Data Width Converter IP

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A further piece of information for you: I tried another axis_dwidth_converter customization, this time accepting all the default parameter settings. The exmple project still gives the same simulation error:

 

ERROR: [XSIM 43-3225] Cannot find design unit xil_defaultlib.exdes_tb in library work located at xsim.dir/work.

 

PaulD

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Adventurer
Adventurer
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Registered: ‎03-05-2008

Re: Simulation error on example design for AXI Data Width Converter IP

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Hello Ashish,

 

I tried your workaround but had problems. 

 

1) There isn't a file called axi_register_slice_v2_1_axi_register_slice.v ... but there is a similarly named one called axis_register_slice_v1_1_axis_register_slice.v. 

 

2) You mentioned the file axi_infrastructure_v1_1_header.vh ... but there isn't one in the project.

 

3) At line  #132 of  axis_register_slice_v1_1_axis_register_slice.v. there is an include line:

 

`include "axis_infrastructure_v1_1_axis_infrastructure.vh"

 

I changed this line to have an absolute path (206 characters long) ... and tried simulation ... and got the same error message as before.

 

4) I then did a string search for all occurences of the same include line in any .v file in the project ... and changed them for absolute paths ... ... and tried simulation ... and this time it worked.

 

I'm going to repeat the workaround on a new project because I'm not sure if all the changes I made were necessary.

 

 

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Adventurer
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Re: Simulation error on example design for AXI Data Width Converter IP

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Hello Ashish,

 

I've now repeat the workaround on a new project ... making changes to 7 verilog files giving them absolute paths to the verilog header file ... and simulation now runs.

 

Is there not an easier way to do this? I'm thinking of a serach path directive for finding verilog header files.

 

Kind regards

PaulD

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Xilinx Employee
Xilinx Employee
18,886 Views
Registered: ‎02-14-2014

Re: Simulation error on example design for AXI Data Width Converter IP

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Hello @prdorrell,

 

I can see two files in below folder <project_directory>/axi_dwidth_converter_0_example/axi_dwidth_converter_0_example.srcs/sources_1/ip/axi_dwidth_converter_0/axi_register_slice_v2_1/hdl/verilog/

 

The files are 

 

axi_register_slice_v2_1_axi_register_slice.v

axi_register_slice_v2_1_axic_register_slice.v

 

and when I just changed the path of header file in axi_register_slice_v2_1_axi_register_slice.v at line #211, simulation worked for me.

 

Anyways we can conclude that finding the path of header file was the issue. Once you provide absolute path, the simulator is able to pick it and complete the simulation.

 

Currently you can proceed with this workaround. As I mentioned, CR is filed for this issue and appropriate enhancements will be made in future release.

Regards,
Ashish
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Give Kudos to a post which you think is helpful and reply oriented.
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Visitor
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Registered: ‎06-19-2016

Re: Simulation error on example design for AXI Data Width Converter IP

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The vivado xsim commond 'xvlog' can't find include file 'axis_infrastructure_v1_1_0_axis_infrastructure.vh' while compile the file axis_register_slice_v1_1_axis_register_slice.v, because the .vh file path's length is too long. 

The simplest way to fix this problem is:

1)copy axis_infrastructure_v1_1_0_axis_infrastructure.vh file to the sim folder: project_name.sim\sim_1\behav\

2)In vivado simulation tab: don't clean up sim files in order not to delete the .vh file

3) launch simlulation...

 

This is OK for me when compile the aurora 64/66 ip example using vivado 2016.2 

 

 

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