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Adventurer
Adventurer
414 Views
Registered: ‎08-22-2019

Simulation error

Hi xilinx team. Below is that attachment. I just built one simple VHDL program and test bench. It was running fine before and I able to see the simulation wave forms too. But once after i saved the wave form I could not able to run the simulation again it is throwing an error like this please refer the attachment. I deleted the file which saved and ran again but still I cannot over come with that issue.. How do I solve this buddies please let me know ? And I am using vivado 19 series. Thanks at the earliest.
IMG20200216181524.jpg
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6 Replies
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Scholar
Scholar
404 Views
Registered: ‎08-07-2014

Re: Simulation error

@mubasheerahmed_12,

As the message box says, did you check the TCl Console or log file?

What info is in there?

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Adventurer
Adventurer
401 Views
Registered: ‎08-22-2019

Re: Simulation error

It says failed to launch simulation due to earlier errors.
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Contributor
Contributor
373 Views
Registered: ‎10-25-2019

Re: Simulation error

Can you attact the log file or source code of it? If it was working fine previously then I suggest you to reset the simulation or close the vivado and any of its instance from task manager and delete .sim directory and run the simulation again .

Feel free to accept as solution if it solves your issue.

Regards,
jagannath@logictronix.com
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Adventurer
Adventurer
365 Views
Registered: ‎08-22-2019

Re: Simulation error

Hi. I followed as you said. I did reset my test bench. Now finally I deleted my simulation folder from the project and creating I hope that will work now but, if I ever encounter the problem like this in future how to resolve. When I lunch behavioral simulation and error pops up saying launching simulation failed due to an earlier error same thing even in the console says this test case was running before but once after savings wave form this error started. I am sorry in my phone I don't know why I cannot tag more than 1 picture to show you my problem I hope I have tried best to explain. Thanks for your reply.
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334 Views
Registered: ‎01-22-2015

Re: Simulation error

@mubasheerahmed_12 

Yes, tracking down simulation errors is a little unusual.

As the initial dialog box says you must first open the Tcl Console.  There, the last few lines are not helpful.  However, you only need to scroll up in the Tcl Console to find the real errors - as shown in my screenshot below.

Also, you cannot just click on the error messages in the Tcl Console to automatically open the file and go to the line with the error.  Instead, you must manually open the file and manually scroll to the line with the specified line number.  In the screenshot example shown below, I had to open the file called TOP.vhd and scroll to lines 133 and 145 to find the error.

sim_error.jpg

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Adventurer
Adventurer
326 Views
Registered: ‎08-22-2019

Re: Simulation error

Yes that's right.thank you Sir. I got your point! And there is one more problem started here. When I launch my SDK in SDK log one error occurred says hardware cannot be specified and when I looked in to the details it said my file access denied then I check the directory which was restricted and applicable only for read only in Windows 10 but any how I dunno how I can still able to go ahead and create my boot.bin file but here another thing I saw is to generate boot.bin I dunno why my . bit file has not reflected but still can able to create my boot.bin with .bif and .elf file. If I am not clear in explanation now, I will post this tomorrow with screen shots with new thread. Thank you for the reply
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