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David_D
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Registered: ‎02-11-2021

Simulation fails, Tcl console displaying "index value <0> is out of range [1:2147483647] of array "

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Hello,

I am using Vivado 2019.2 and, for my project, I need to have arrays as inputs of my final top_module file.

As I could not find a way to do it in VHDL-93, I have used VHDL 2008 and create a package where I have defined the types I would use for those arrays. I have also changed the type of all my files to VHDL 2008

I have synthesized several time to make sure there would be no problem and, when I'm launching simulation, it fails and return this :

"index value <0> is out of range [1:2147483647] of array <coef_array> "

I have run out of idea on how to resolve this. Can you help me ?

I am attaching the package file and the file using it, as well as the testbench so you can see how I wrote it

Regards,

David

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richardhead
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Registered: ‎08-01-2012

Yes - XSIM (including 2020.2) is basically a terrible VHDL simulator. Its only been 13 years, which clearly isnt enough time for Xilinx to support VHDL 2008 properly. But to make life even more complicated, the synthesis has much better (actually quite good as of 2019 versions) 2008 support.

Free alternatives exist - you can get the FOSS GHDL: http://ghdl.free.fr/

you can also get the free version of intel modelsim (Xilinx Competitor) from here. It has had VHDL 2008 support for about 10 years: https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/model-sim.html

The Best (paid for) simulator in terms of support are Aldec's tools. Rivera Pro has had some VHDL 2019 support for a few months, and Active HDL since 12.0: https://www.aldec.com/en/products/fpga_simulation/active-hdl

If I went for a job interview, and I was told I only had access to the Xilinx simulator, I likely wouldnt take the Job.

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David_D
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Registered: ‎02-11-2021

Update: I have now used generics in my package so that I could manage the size of my new type more easily. Now, when I want to synthesize, it fails and returns:

"[Synth 8-4760] uninstantiated package cannot be specified in use clause ["C:/Users/David/Documents/FPGA/upwork/RCCM/RCCM/Matrix_mult.vhd":9]"

I have no idea of how I should proceed from that...

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richardhead
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Registered: ‎08-01-2012

You have declared the coef_array  type to use a positive - this requires the ranges to be between 1 and 2**31. You started the range at 0, hence why you get the error. Did you really want a minimum index of 1?

As for the generic package, this is VHDL 2008. If you put a generic on a package, you first need to create an instance of the package with the generics set, or left at default. You would then use the instantiated version of the package.

so in your case:

 

package TYPES_size_8_pkg is new TYPES generic map(size => 8);

-- and in the matrix_mult:
use work.TYPES_size_8_pkg.all;

 

David_D
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Registered: ‎02-11-2021

Thank you for your answer, I have trouble understanding where I should declare the instantiation 

- If I put it in my architecture(matrix_mult), I will not be able to use my new types in my entity;

- When I put the instantiation in the package file, which I found weird, and put the use clause in matrix_mult, Vivado would return an error;

- I have no knowledge of instantiation being made outside the architectecture. Maybe it's were I got it wrong...

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richardhead
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Registered: ‎08-01-2012

Package instances can be root objects, ie. they can be decalred in a library. They can also be decalred inside architecture, or processes and the scope will alter accordingly. For example, you could simply instantiate the package after the package body.

 

 

David_D
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Registered: ‎02-11-2021

Hey, thank you for your help !

I have instantiated my package before my entity Matrix_mult and the Synthesis went smooth. The problem is again in the simulation.

As soon as I launch it, the Tcl Console displays:

ERROR: [XSIM 43-4187] File "C:/Users/David/Documents/FPGA/upwork/RCCM/RCCM/TYPES.vhd" Line 12 : The "Vhdl 2008 Unconstrained Array Type as Subtype in Array Type Definition" is not supported yet for simulation.

I went through some forums that redirected me to UG900 Vivado Logic Simulation User Guide. From there, I could see that generic in a package was not supported by XSIM. I decided then to change my type declaration to not include generic but under the form:

type bus_array is array(natural range<>) of SIGNED;
type coef_array is array (natural range<>) of STD_LOGIC_VECTOR(3 downto 0);

 

I changed the way Matrix-mult is connected to it then ran Synthesis again. No errors but simulation fails again with the same error. I thought that this feature was accepted according to the table C-1...

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richardhead
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Registered: ‎08-01-2012

Yes - XSIM (including 2020.2) is basically a terrible VHDL simulator. Its only been 13 years, which clearly isnt enough time for Xilinx to support VHDL 2008 properly. But to make life even more complicated, the synthesis has much better (actually quite good as of 2019 versions) 2008 support.

Free alternatives exist - you can get the FOSS GHDL: http://ghdl.free.fr/

you can also get the free version of intel modelsim (Xilinx Competitor) from here. It has had VHDL 2008 support for about 10 years: https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/model-sim.html

The Best (paid for) simulator in terms of support are Aldec's tools. Rivera Pro has had some VHDL 2019 support for a few months, and Active HDL since 12.0: https://www.aldec.com/en/products/fpga_simulation/active-hdl

If I went for a job interview, and I was told I only had access to the Xilinx simulator, I likely wouldnt take the Job.

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David_D
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Registered: ‎02-11-2021

Thank you so much!

I had a previous encounter on the Xilinx forum with a scholar and a moderator, who were quite condescending when I ask if I could use the intel edition of Modelsim to simulate my mode (which contains UNISIMS libraries). So I thought I was stuck using XSIM !

And yeah, I will likely not use XSIM in my future, it's so restrictive

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richardhead
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Registered: ‎08-01-2012

Using Xilinx libraries in Intel modelsim might be harder, but might be possible (I havent tried)

I dont work for Xilinx. I luckily have ActiveHDL.

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