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Observer serge1973
Observer
7,422 Views
Registered: ‎09-13-2015

Simulation failure for counters

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Hi,

I'm trying to build a counter which is part of my project to build a logic for an FPGA that will implement an analog clock with an hour hand and a minute hand that is displayed on VGA screen.

I have three files:

1. Counter that contains the logic for the counters (one to counte horizantally and the other vertically)

2. Clock file which contains component declaration and the instantiation

3. the third file is for benchmark (or test bench).

I'm currently having issue with clock file where I don't seem to instantiate and do the port mapping correctly. It's saying for example that one <ena> is not declared. I don't know yet about the other two files but Xilinx ISE seems to simulate or check syntax one file at the time and once it's found an error it won't proceed to the others. I could be wrong.

 

Thanks for your help!

 

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Instructor
Instructor
14,337 Views
Registered: ‎08-14-2007

Re: Simulation failure for counters

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The point is that the generics and ports of an entity need to match those of the instantiation.  This error shows that you are trying to set generics "hor" and "ver" for entity counter, but that entity is defined as:

 

entity counter is
  generic (rollover: integer := 800);
  port (clk   : in  STD_LOGIC;
        rst   : in  STD_LOGIC;
        ena   : in  STD_LOGIC;
        q_out : out STD_LOGIC_VECTOR(9 downto 0));
end counter;

 

As you see there is only a "rollover" generic, not "hor" or "ver".

 

Yet here is your instantiation in clock.vhd:

 

--instantiate, generic and  port map for counter
begin
  U1: counter
    generic map (
      hor => 800,
      ver => 525)
    
    port map (
      clk   => clk,
      rst   => rst,
      ena   => ena,
      q_out => q_out);

 

-- Gabor

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4 Replies
Instructor
Instructor
7,417 Views
Registered: ‎08-14-2007

Re: Simulation failure for counters

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entity clock IS
  port (clk   : in  STD_LOGIC;
        rst   : in  STD_LOGIC;
        q_out : out STD_LOGIC_VECTOR(9 downto 0));
end clock;

 

Looks like you forgot to add an ena input port to the clock.vhd entity.

-- Gabor
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Observer serge1973
Observer
7,406 Views
Registered: ‎09-13-2015

Re: Simulation failure for counters

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Hi @gszakacs,

Thanks!

Do you know if I need to reinstantiate the port in my tesyt bench file? When I comment them out it's fine but now there's another error generated in clock file which say:

 

ERROR:HDLCompiler:244 - "/home/serge/Documents/FPGA_Course/HW3/HW3/../clock.vhd" Line 25: Binding entity counter does not have generic hor
ERROR:HDLCompiler:244 - "/home/serge/Documents/FPGA_Course/HW3/HW3/../clock.vhd" Line 26: Binding entity counter does not have generic ver
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit clock in library work failed

 

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Instructor
Instructor
14,338 Views
Registered: ‎08-14-2007

Re: Simulation failure for counters

Jump to solution

The point is that the generics and ports of an entity need to match those of the instantiation.  This error shows that you are trying to set generics "hor" and "ver" for entity counter, but that entity is defined as:

 

entity counter is
  generic (rollover: integer := 800);
  port (clk   : in  STD_LOGIC;
        rst   : in  STD_LOGIC;
        ena   : in  STD_LOGIC;
        q_out : out STD_LOGIC_VECTOR(9 downto 0));
end counter;

 

As you see there is only a "rollover" generic, not "hor" or "ver".

 

Yet here is your instantiation in clock.vhd:

 

--instantiate, generic and  port map for counter
begin
  U1: counter
    generic map (
      hor => 800,
      ver => 525)
    
    port map (
      clk   => clk,
      rst   => rst,
      ena   => ena,
      q_out => q_out);

 

-- Gabor

View solution in original post

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Observer serge1973
Observer
7,386 Views
Registered: ‎09-13-2015

Re: Simulation failure for counters

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Got it. Thanks!

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