Simulation for FIFO with MIG-DDR3 controller

[huyhl248]

Dear community,

I am a bit newbie in FPGA and Xilinx. I have a project that implementing a FIFO on Kintex 7. Because of some reasons, I have to use an external DDR3 to save data.

I found this tutorial on the Internet (It connect 2 buffer standard FIFOs to a logic module, then connect to an external DDR3 via AXI4 MIG) and I modified it to match with my requirements by :

- Customizing DDR3 MIG IP(using MT4KTF25664HZ-1G9 - SODIMMs, AXI4 enabled).

- Adding 2 standard 512x16 FIFO IPs by FIFO Generator.

- Run synthesis and implementation properly.

My question is how to implement the simulation? Do I need a DDR3 model, connect it to MIG, then create a simple testbench for my FIFO? I tried generating example_top for MIG but I don't know how to simulate if MIG connects to another modules.

Thank you very much!

Best regards,

Charlie.

[huyhl248]

Update: I found ddr3_model.v in MIG example module. I plan to use FIFO generator simulation module as my skeleton. However, FIFO generator vivado 2018.3 only generated vhd instead of verilog. How do I get verilog?

[ryana]

Hello @huyhl248 ,

I would check to see which languages are supported by the IP but the other thing to do is check the Project and Simulation Language settings.
Here go to the Settings button under the Project Manager portion of the Flow Navigator and in the General tab you can select your language:

Next you can go to the Simulation section and select the language there:

Once again you may be limited by the supported output product language by the IPs in your design.

[huyhl248]

Hi @ryana ,

Thanks for your response!

It is only right for MIG. FIFO generator on vivado 2018.3 only generates vhd code (after I right click on IP and choose 'Open IP example...') although I set 'verilog' for Target language anf Simulation language!

Please have a look!

Thank you!