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jaruiz@kaleao
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Registered: ‎11-28-2018

Simulation libraries for FIFO generator

Long story short: I have inherited a piece of unpackaged IP built around Xilinx' DMA IP. I have a bunch of vhdl files but no xci. Also I have no documentation, notes or any information from the people who wrote this. I think a version of this block has been used in a BD project but I'm not sure and I have no examples to examine.

I am now trying to instantiate that block in an unrelated test bench (which is not a BD but regular HDL) but I get errors because the vhdl files make use of library "fifo_generator_v13_0_1". That library is not included in the sources I have but I *think* it can be generated from Vivado as part of the simulation sources of a project that uses it.

Apparently the files I need are "fifo_generator_vhdl_beh.vhd" and "fifo_generator_v13_0_rfs.vhd".

 

My question is: how can I get a copy of those files?

(Please note that my version of Vivado ships with version 13.1 of the FIFO generator core.)

 

Any help will be very much appreciated!

 

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jaruiz@kaleao
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Registered: ‎11-28-2018

I should add that I have been able to scavenge copies of those files from the internets and it looks like they will do the trick. But this looks jury-rigged.

What's the proper way to deal with a situation like this?
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jaruiz@kaleao
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Registered: ‎11-28-2018

So far I have managed to get the build to work by adding a bunch of files I have found on the internet.

These include "fifo_generator_v13_0_rfs.vhd" and "blk_mem_gen_v8_3_vhsyn_rfs.vhd". With those big, encrypted files in the project there are no black boxes and all build dependencies are satisfied.

 

But I'm pretty sure those files have been generated for a particular configuration of some IP block or other. In other words, I suspect they are not generic; otherwise Xilinx would make them easily available.

I have no idea where to look for info about this. Is this stuff addressed specifically by any document? Plowing through the TCL manual and other user guides has not helped me so far...

 

I should probably add that, although my TB build finishes with no errors, I do get this (repeatably) when the simulation starts:

 

     ERROR: [XSIM 43-3316] Signal SIGSEGV received.

 

With that info I am doing my best to diagnose the issue but it may take me a while. Any help will be very very much appreciated!

 

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amaccre
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Registered: ‎04-24-2013

Hi jaruiz@kaleao,

Version 2015.4 of Vivado is the first to include a copy of the fifo generator version 13.1

* Version 13.0 (Rev. 1)
* Fixed safety circuit related warnings in Behavioral model
* Revision change in one or more subcores

You could get a copy of this and regenerate the IP with the output products.

Alternatively you could upgrade your project to a modern version of the tools and upgrade the IP via report_ip_status.

Best Regards
Aidan

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