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Adventurer
Adventurer
4,449 Views
Registered: ‎04-07-2011

Simulation mismatch in behavioral and par

Hi friends

 

I am facing an issue and am not able to crack it down.

 

I ahve  a bidirectional input named DATA. I use DIR as the control signal. When DIR is high, the value of DATA is given as an input to the module, else it is loaded with the signal value DATA_OUT.

 

Here is a snippet of the code

This is doen in the wrapper file

DATA_IN <= DATA ;
 DATA <= DATA_OUT WHEN DIR = '0' ELSE
         (OTHERS => 'Z');

 

another snippet of the state machine with data_out part. This is in the submodule which has DATA_Ina nd DATA_out as inputs and outputs mapped from the top level above

 

 

 IF (CLK'EVENT AND CLK = '1') THEN
         IF (RESET = '1') THEN
            TX_PSTATE <= TXIDLE1;
                        DATA_OUT <= (OTHERS=> 'Z') AFTER 1 NS;
                     ELSE
            -- Default Assignment To Internals and Outputs
                        -- Combined Actions
            CASE TX_PSTATE IS
               WHEN TXIDLE1 => 
                      DATA_OUT <= (OTHERS => 'Z') AFTER 1 NS;

 

 

 

 

Now when as soon as DIR = '0' the DATA_OUT value is made (others => '0') after which it is made x"ZZ". When DIR is high, the required data packet is inputted to the module through DATA input port(Input mode of I/o).

 

In Behavioral, it works just fine. However, when I run a PAR simulation, the DATA_OUT value becomes "FF" instead of "ZZ". There are no multidriving signals for DATA_OUT so I am not able to understand why this could be happening.

 

I am attaching the snapshots of both behavioral and PAR simulation for easy clarity. Please help me out guys. I am in a fix.

 

Looking forward to your reply

 

 

akanksha

 

beh_data.bmp
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4 Replies
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Adventurer
Adventurer
4,443 Views
Registered: ‎04-07-2011

Re: Simulation mismatch in behavioral and par

the par simulation snapshot

par_data.bmp
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Historian
Historian
4,432 Views
Registered: ‎02-25-2008

Re: Simulation mismatch in behavioral and par

You do realize that in a statement such as:

 

 

 IF (CLK'EVENT AND CLK = '1') THEN
         IF (RESET = '1') THEN
            TX_PSTATE <= TXIDLE1;
                        DATA_OUT <= (OTHERS=> 'Z') AFTER 1 NS;
                     ELSE
            -- Default Assignment To Internals and Outputs
                        -- Combined Actions
            CASE TX_PSTATE IS
               WHEN TXIDLE1 => 
                      DATA_OUT <= (OTHERS => 'Z') AFTER 1 NS;

 

that the "after 1 ns" is ignored by the synthesis tool?

----------------------------Yes, I do this for a living.
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Adventurer
Adventurer
4,419 Views
Registered: ‎04-07-2011

Re: Simulation mismatch in behavioral and par

hey hi

ya i do

 

but could you please elaborate on the point. I could not co-relate my query with your answer.

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Teacher
Teacher
4,415 Views
Registered: ‎08-14-2007

Re: Simulation mismatch in behavioral and par

Hi,

first of all, if Data is bidirectional  it isn't just an "input", that's contradicting. You probably meant "port" there.

I assume Data is connected to the PADs of the FPGA, being connected with the PCB and external circuits, right?

 

 

When you have a wrapper that accesses the unidirectional ports Data_In and Data_Out and combines them into the Data port controlled by Dir, then it is not neccessary to assign 'Z' to Data_Out in your State machine. Actual FPGAs have no internal tristate drivers anymore. Only exception is, when you have several drivers for Data_Out. Then internally a Mux is created by such a coding. While the behavioral simulation might show "Z"s then, the PAR simulation might just show you '1's and '0's.

 

Your simulations show lots of signals, but unfortunately not all the interesting ones.

Both sims should show these signals:

Dir

Data

Data_In

Data_Out

 

When you look at Data of your Behavioral Sim. there are events, where it goes to "00" shortly after Dir goes low.

This is the expected Data to appear at data Out? Probably because your FSM assings these 'Z's.

 

Now in the PAR-Sim. Data_Out never has a 'Z'. Probably because the created internal muxes are not able to create one.

Therefore Data will show these values too when DIR is low.

You see that the IOBs tristate driver for Data is working correctly, since between the falling edge of Dir and the next falling edge of Clk Data is 'Z'.

 

To my opinion, everything seems to be OK with the simulations. Only thing you should investigate is the small red part of the Data waveform. Are there just 'Z' mixing with real data or are there 'X's?

 

Have a nice simulation

  Eilert

 

 

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