Simulation of IP Core using ModelSim

[bouali_yacine]

I try to use IP core in Xilinx ISE 14.2. When the simulation done with ISim it works fine. Now I need to do the simualtion with ModelSim SE-64 10.7.

1. I compile HDL Simualtion Libraries Fig.1.

2. I run the simulation with ModelSim but it give me the error 

# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec  7 2017
# Start time: 18:17:16 on Sep 03,2020
# vcom -reportprogress 300 -explicit -93 ipcore_dir/CoreAdder.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity CoreAdder
# -- Compiling architecture CoreAdder_a of CoreAdder
# ** Error: (vcom-11) Could not find xilinxcorelib.c_addsub_v11_0.
# ** Error (suppressible): ipcore_dir/CoreAdder.vhd(66): (vcom-1195) Cannot find expanded name 
  "xilinxcorelib.c_addsub_v11_0".
# ** Error: ipcore_dir/CoreAdder.vhd(67): (vcom-1105) Name (indexed name) does not denote an 
entity name.
# ** Error: ipcore_dir/CoreAdder.vhd(66): Unknown expanded name.
# ** Note: ipcore_dir/CoreAdder.vhd(108): VHDL Compiler exiting
# End time: 18:17:16 on Sep 03,2020, Elapsed time: 0:00:00
# Errors: 4, Warnings: 0
# ** Error: C:/modeltech64_10.7/win64/vcom failed.
# Error in macro ./tb_MYAdder.fdo line 23
# C:/modeltech64_10.7/win64/vcom failed.
#     while executing
# "vcom -explicit  -93 "ipcore_dir/CoreAdder.vhd""

1. The name of the toplevel is: MYAdder.
2. The name of the testBench is: tb_MYAdder.
3. The name of the ip Core in my project :CoreAdder.

                         Fig.1

[graces]

If you compiled the simulation libraries successfully, there would be compxlib.log as well as modelsim.ini in the target directory. Ensure xilinxcorelib is included in modelsim.ini. Also ensure modelsim.ini is copied to the simulation directory (project directory in this case).