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Newbie dhmitris
Newbie
3,611 Views
Registered: ‎05-07-2012

Simulation problem - Input is not taken into account during the positive edge

Hello, 

 

Im implementing tomasulo's algorithm as an undergraduate project.

 

This is the permision to write to the cdb bus code :

 

process
begin
	wait until clk'event and clk='1';
	if Rst='1' then
		state<="00";
		Full<='0';
		Enable<="00";
	else
		--1st state--
		if Ask='1' and state="00" then	--Cold start
			Enable<="11";
			ask_perm<='1';
			Full<='0';
			state<="10";--change state to the next state
			
		--End of 1st state--
		
		--2nd state with permision granted--
		elsif state="10" and Granted='1' then --asked for permision and it was granted
			Full<='0';
			Enable<="11";
			
			if Ask='1' then	--Next commmand in the pipe wants access
				ask_perm<='1';
				state<="10";	--back to 2nd state
			else
				ask_perm<='0';
				state<="00";	--back to 1st state
			end if;
		

 There is more code after this, the problem is here :

 

prob.png

 

as you can see, i lose 1 clock cycle to see change the output, in previous versions  and with other projects this problem did not occur. Is there a setting to make the simulation take into account input changes that occur during the positive edge?

 

Thanks in advance.

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2 Replies
Scholar austin
Scholar
3,604 Views
Registered: ‎02-27-2008

Re: Simulation problem - Input is not taken into account during the positive edge

d,

 

ASK went high exactly at the same time clock went high.  Thus, on the edge, it can't be "seen."  Real logic requires a setup time, and often a hold time.

 

In simulation you can create conditions that may never actually happen.


But, if they did, it would work exactly as it shows.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Historian
Historian
3,596 Views
Registered: ‎02-25-2008

Re: Simulation problem - Input is not taken into account during the positive edge

Welcome to Synchronous Logic Design 101.

 

A functional simulation shows what appears to be signals changing instantly with the clock. In reality, the signal changes a delta cycle after the edge of the clock, after all right-hand-sides of assignments are worked out. The delta cycle is a VERY important concept in HDL simulation, so you MUST understand it.

 

So what happens is that on clock cycle X, your flip-flop's output signal changes from (say) 0 to 1. You have to wait until the next clock cycle to actually use that new flop output value. 

 

Now say for instance that you want to use the value of a signal foo. What happens is that on the rising edge of the clock, all currently-assigned values on each signal, like foo, are used on the right-hand-side of all assignments. So, in other words, it's the value on each signal, like foo, immediately before the clock edge. foo is likely the target of an assignment, so its value may change, but it won't change until after the clock edge and all right-hand-sides are evaluated.

 

Of course, real hardware has a non-zero clock-to-out delay. This means that instead of the output changing immediately with the clock (as it appears in a functional simulation), it changes some time afterwards. (Back in the day of slow HCT logic, it could be several nanoseconds!) On a waveform display, that change is very obvious, and it's also obvious, therefore, what is sampled when the clock edge occurs.

 

So that all explains why you have a one-clock delay. You can't assign a signal on an edge, and use its new value on that same edge.

----------------------------Yes, I do this for a living.
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