09-26-2014 08:09 AM
Hi people, I have a problem with a simulation of sequential circuit. I have a simple D Flip-Flop and I selected it for shematic project, connect the input, clock and output. Then, I created a new test bench in verilog for shematic circuit, and the waveform of the output is wrong. Then i wrote in verilog code the sehematic circuit and simulte using the same testbench and the wavefroms are corrects. I dont know if i need configurate anything for simultion if the the project is en shematic circuit.
09-26-2014 01:15 PM
"The waveforms are wrong" doesn't give much to go by. However, the first thing that comes to mind is that when using schematic elements like FDCE for example, you are using a simulation model that includes GSR (global set/reset). By default this signal is high for the first 100 ns of simulation, so any stimulus to the flip-flop before 100 ns has elapsed will not affect the output.
09-27-2014 02:09 PM
Thanks for the answer, this is my problem, when the flip-flop set the output only 100ns after. I don´t know how I disable the GSR of the flip-flop.... if you know help please...
09-28-2014 06:34 AM
You don't disable GSR. It is a fact of life. The simulation drives it for 100 ns by default, and you could change this behavior by over-driving the signal from your own test bench (the default driver is a weak 1). However it's generally easier to just pretend those first 100 ns don't exist and start you stimulus afterwards.
In the real hardware, GSR is released before GWE (global write enable) which means that the flip-flop can't get any stimulus in real hardware until well after GSR is released. It's not clear why Xilinx felt it necessary to assert GSR for 100 ns in simulation. I would have thought that just initializing the sequential elements at time zero within the simulation model would have been enough to simulate power-on configuration. And assuming you don't insert a STARTUP block in your own code, there's no way that GSR would be re-asserted after configuration completes.