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Registered: ‎03-17-2019

Simulation troubles in Vivado

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Hi

I am doing a projet which is creating a single cycle mips processor. I have a testbench which reads data from a log file created in Pc-spim, the test bench just fills up the the instruction memory.

When I try to simulate it in Vivado i get this error:

ERROR: [VRFC 10-1537] value 4294901760 is out of target constraint range -2147483648 to 2147483647 [/proj/xhdhdstaff2/tapodyu/XsimWork/data/vhdl/src/synopsys/compileToIeee/std_logic_arith.vhd:2434]

Anyone knows what it might be or a way to get more info about what may cause it?

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Simulation troubles in Vivado

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elt13jjo@student.lu.se 

Why not post some code?

I suspect you're trying to convert a 32bit unsigned value to an integer. Integer is defined as -2**31+1 to 2**31-1, so a 32 bit unsinged cannot be converted to an integer type. I bet you did something like this:

signal addr : std_logic_vector(31 downto 0);
....
conv_integer(addr); -- 32 bits unsigned overflows the base integer type

I also bet you're actually using std_logic_unsigned - this uses std_logic_arith internally for the unsigned/signed types, hence why the error appears to come from there.

Things to do:

1. Use numeric_std like @drjohnsmith  suggests. Although this wont fix the integer overflow problem

2. Dont try and convert a 32 bit unsigned value to integer.

 

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Voyager
Voyager
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Registered: ‎03-28-2016

Re: Simulation troubles in Vivado

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It appears that the input value (4294901760) is an unsigned 32-bit value and the target location is a signed 32-bit value.  You might need a 33-bit target location or you might need to cast the input value as a signed value.

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
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Teacher
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Registered: ‎07-09-2009

Re: Simulation troubles in Vivado

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well, well ignore the fact your using that std_logic_arith thing....  it should be dumped AFAIC,

 

What its saying is you have read in a unsigned of value 429....   , and your code is expecting a singed vlaue in the range +- 2147...

 

VHDL is strongly typed, a signed is different to an unsigned.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Registered: ‎03-17-2019

Re: Simulation troubles in Vivado

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Yeah, I got the feeling that it meant something like that. The problem is just that it is ton of vectors in that range that might be causing.

It says something about a code line in the std_logic_arith.vhd:2434. Do you know if it is possible to open that library in Vivado, for seeing what arith. operation who might cause the the problem, it would have narrowed down the search alot? 

What do you recommend instead of the arith?

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Simulation troubles in Vivado

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opening the library will tell you nothing more than already said,

   the genral way of sorting this is to dvide an conqour. cut out half the vectors,

      if it still fails, cut in half again,

my bet is its the very first vector thats causing the problem.

 

as for what libs to use

these are the two basic you should have

library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

 

lots if articles on why, do a search, e.g.

https://www.nandland.com/articles/std_logic_arith_vs_numeric_std.html

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Simulation troubles in Vivado

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elt13jjo@student.lu.se 

Why not post some code?

I suspect you're trying to convert a 32bit unsigned value to an integer. Integer is defined as -2**31+1 to 2**31-1, so a 32 bit unsinged cannot be converted to an integer type. I bet you did something like this:

signal addr : std_logic_vector(31 downto 0);
....
conv_integer(addr); -- 32 bits unsigned overflows the base integer type

I also bet you're actually using std_logic_unsigned - this uses std_logic_arith internally for the unsigned/signed types, hence why the error appears to come from there.

Things to do:

1. Use numeric_std like @drjohnsmith  suggests. Although this wont fix the integer overflow problem

2. Dont try and convert a 32 bit unsigned value to integer.

 

View solution in original post

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Registered: ‎03-17-2019

Re: Simulation troubles in Vivado

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That explains alot. I am using the the conversion from std_logic_vector to integer. Then I know what to look for. 

I will keep to that. Huge thanks for the help guys!

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