02-22-2018 12:35 AM
Hi I have a project in Vivado and it correctly generates the simulation scripts etc and simulates well with Questa.
The problem however arises when we choose Riviera-PRO. Following are the issues:
1) The PCIE IP that we use, generated from IP integrator, has some VHDL files. The library.cfg generated for the riviera simulation doesnt have the unisim path, causing a compilation error.
This problem has a workaround: I have the pre compiled libraries stored in a location outside the project. I simply copy the library.cfg that is pointing to all the pre compiled libraries at this location and while doing the launch_simulation i give the option to not cleanup the directory. So a fresh library.cfg is not generated and the one that i kept gets used. So this problem of VHDL files gets solved.
2) Second issue is that the tb_core_compile.do file that is generated as part of simulation scripts points to files at incorrect location.
eg it looks for a file at <project_name>.srcs/sources_1/ip/axis_data_fifo_0/hdl/axis_infrastructure_v1_1_vl_rfs.
Directory <project_name>.srcs/sources_1/ip exists but it only has .xcix files. There is no axis_data_fifo_0 or any other IP directory at all. I dont know why the compile.do file is looking at incorrect location.
Those files are present in <project_name>.ip_user_files/ipstatic/hdl/ and
To solve this i have to do a find and replace in the compile.do file and get the compilation pass MANUALLY.
3) Because of errors in 1 and 2, the simulate.do file is not even generated. I have to simulate using Questa and copy the vsim command from its simulate.do file to simulate things on Aldec Riviera-PRO which then works fine.
Request Vivado to please fix the Riviera-PRO simulation flow.
The amount of hack is just too much.
Thankyou very much
02-27-2018 08:17 AM
While Aldec Riviera can be used with Vivado and is a supported flow, support for it is provided via Aldec and not by Xilinx.
Aldec will work with Xilinx to fix any compatibility issues
This is documented in User Guide 973