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Adventurer
Adventurer
1,317 Views
Registered: ‎12-26-2016

Simulator with DSP Element stops at 0 fs

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Hi there,

 

to get more familiar with the Zynq and VHDL I try to get more into the usage of DSP slices. I created an entity which accepts N in and outputs (all of type std_logic_vector) which applies a multiplication to a selected signal. The DSP macro is from the language template and adapted to the situation.

 

Sadly the Vivado2017.2 simulator is stuck at 0fs simulation time. The build is successful.

 

Here is the code of my entity

library ieee;
use ieee.STD_LOGIC_1164.ALL;
package multipledata is
    constant NATURAL_BUS_WIDTH : integer := 2;
    constant NATURAL_DATA_WIDTH : integer := 2;
    type data is array(natural range <>) of std_logic_vector(NATURAL_DATA_WIDTH-1 downto 0);
end package;

library ieee;
use ieee.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
use work.multipledata.all;

entity demultiplexer_dsp is 
    generic( bus_width : integer := NATURAL_BUS_WIDTH;
            data_width : integer := NATURAL_DATA_WIDTH);
    port(
        i : in data(bus_width-1 downto 0);
        factor : in std_logic_vector(data_width-1 downto 0);
        clock : in std_logic;
        clock_enable : in std_logic;
        selection : in integer range 0 to bus_width;
        o : out data(bus_width-1 downto 0));
end demultiplexer_dsp;

architecture Behavioral of demultiplexer_dsp is
    signal reset : std_logic := '0';
    
    signal a : std_logic_vector(data_width-1 downto 0) ;
    signal p : std_logic_vector(2*data_width-1 downto 0) ;
    
    constant dsp_latency : integer := 3;
    
begin

MULT_MACRO_inst : MULT_MACRO
   generic map (
      DEVICE => "7SERIES",    -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6" 
      LATENCY => dsp_latency,           -- Desired clock cycle latency, 0-4
      WIDTH_A => data_width,          -- Multiplier A-input bus width, 1-25 
      WIDTH_B => data_width)          -- Multiplier B-input bus width, 1-18
   port map (
      P => P,     -- Multiplier ouput bus, width determined by WIDTH_P generic 
      A => A,     -- Multiplier input A bus, width determined by WIDTH_A generic 
      B => factor,     -- Multiplier input B bus, width determined by WIDTH_B generic 
      CE => clock_enable,   -- 1-bit active high input clock enable
      CLK => clock, -- 1-bit positive edge clock input
      RST => reset  -- 1-bit input active high reset
   );
   -- End of MULT_MACRO_inst instantiation
   
   process(selection)
    variable wait_for_dsp : integer := dsp_latency;
    variable index : integer := 0;
   begin
   
   if(selection'event) then
    a <= i(index);
    reset <= '0';
    wait_for_dsp := dsp_latency;
   end if;
   
    for index in 0 to bus_width-1 loop
        if(index = selection and wait_for_dsp <= 0) then
            o(index) <= p(data_width-1 downto 0);
            reset <= '1';
        else
            o(index) <= i(index);
        end if;
        
        wait_for_dsp := wait_for_dsp - 1;
    end loop;
   
   end process;

end Behavioral;

To test the whole thing I created the following testbench

library ieee;
use ieee.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
use work.multipledata.all;

entity demux_mult_tb is
    --
end demux_mult_tb;

architecture behavioral of demux_mult_tb is
    
    constant b_width : integer := 2;
    constant d_width : integer := 2;

    component demultiplexer_dsp is 
    generic( bus_width : integer;
            data_width : integer);
    port(
        i : in data(bus_width-1 downto 0);
        factor : in std_logic_vector(data_width-1 downto 0);
        clock : in std_logic;
        clock_enable : in std_logic;
        selection : in integer range 0 to bus_width;
        o : out data(bus_width-1 downto 0));
    end component;
    
    signal i_tb : data(b_width-1 downto 0);
    signal factor_tb : std_logic_vector(d_width-1 downto 0);
    signal clock_tb : std_logic;
    signal ce   : std_logic;
    signal sel_tb : integer := 0;
    signal o_tb : data(b_width-1 downto 0);
    
begin

mapping: demultiplexer_dsp 
    generic map(bus_width => b_width, data_width => d_width) 
    port map(
                i => i_tb,
                factor => factor_tb,
                clock => clock_tb,
                clock_enable => ce,
                selection => sel_tb,
                o => o_tb
    );
    
    process
        variable step : integer := 0;
        variable index : integer := 0;
    begin
        
        for index in 0 to b_width-1 loop
            i_tb(index) <= std_logic_vector(to_unsigned(0, i_tb(index)'length));
        end loop;
        factor_tb <= std_logic_vector(to_unsigned(0, factor_tb'length));
        clock_tb <= '0';
        ce <= '0';
    
        for step in 0 to 10 loop
            for index in 0 to b_width-1 loop
                i_tb(index) <= std_logic_vector(to_unsigned(step, i_tb(index)'length));
            end loop;
            
            -- start the calculation at step 4!
            if(step = 4) then
                sel_tb <= 1;
            end if;
            
            clock_tb <= clock_tb xor '1';
            
        end loop;
    end process;

end behavioral;

Are there any mistakes I made or is it a problem of the simulator?

 

By the way: I'm not so much familiar with the VHDL code, therefore it migh be a little messy ;)

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Moderator
Moderator
1,763 Views
Registered: ‎04-24-2013

Re: Simulator with DSP Element stops at 0 fs

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Hi @tmaintz,

 

You haven't included any delays / wait statements into your testbench.

Try the code attached and see how you get on.

 

Capture_SIm.JPG

 

Let me know if this helps.

Best Regards
Aidan

 

 

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2 Replies
Highlighted
Moderator
Moderator
1,764 Views
Registered: ‎04-24-2013

Re: Simulator with DSP Element stops at 0 fs

Jump to solution

Hi @tmaintz,

 

You haven't included any delays / wait statements into your testbench.

Try the code attached and see how you get on.

 

Capture_SIm.JPG

 

Let me know if this helps.

Best Regards
Aidan

 

 

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
------------------------------------------------------------------------------------------------------------------

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
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View solution in original post

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Adventurer
Adventurer
1,291 Views
Registered: ‎12-26-2016

Re: Simulator with DSP Element stops at 0 fs

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Thanks! That helped. Now I can debug my code ;)

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