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Historian
Historian
6,885 Views
Registered: ‎02-25-2008

Spartan 3A IBUFDS and IBUFGDS models and their delay generics

On Spartan 3A/AN devices (and maybe 3E, I don't know) one can delay individual inputs somewhat coarsely using the IBUF_DELAY_VALUE (for the asynchronous path) and the IFD_DELAY_VALUE (for the synchronous path) generics on instances of IBUF and IBUFDS. One can also use IBUF_DELAY_VALUE with IBUFG and IBUFGDS.

 

While the simulation models check to see if the values are legal, but otherwise the value of the delays is ignored. Thus a pre-route simulation, where you want to ensure that (say) your clock egde captures source-synchronous data properly, may not work right. 

 

Is there are particularly good reason why? 

 

Could the documentation be updated to include something that says, "Delay values ignored for simulation?" Because that would be swell.

 

(And, please, telling me to do a post-route backannotated timing simulation isn't helpful when trying to design and debug an entity before implementing the entity.)

 

Edit: I opened Webcase 930370 in order to at least get an answer to "why." 

 

Also, the dynamic delay can be modeled. Just not the static delay.

 

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Historian
Historian
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Registered: ‎02-25-2008

Re: Spartan 3A IBUFDS and IBUFGDS models and their delay generics

The google found the following image, associated with AR 31906:

 

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Professor
Professor
6,871 Views
Registered: ‎08-14-2007

Re: Spartan 3A IBUFDS and IBUFGDS models and their delay generics

What version of ISE are you using?  On ISE 13.4 I have a Spartan 3A design with variable delays and

these seem to be modeled correctly during behavioral simulation.  it uses the IBUF_DLY_ADJ primitive.

 

-- Gabor

-- Gabor
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Historian
Historian
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Registered: ‎02-25-2008

Re: Spartan 3A IBUFDS and IBUFGDS models and their delay generics


@gszakacs wrote:

What version of ISE are you using?  On ISE 13.4 I have a Spartan 3A design with variable delays and

these seem to be modeled correctly during behavioral simulation.  it uses the IBUF_DLY_ADJ primitive.

 

-- Gabor


I'm using 14.1 on a Windows box and I looked through the sources provided in C:\Xilinx\14.1\ISE_DS\ISE\vhdl\src\unisims\primitive. All of the buffers I mention do not model the delay.

 

I see the same thing with the unisim library provided by Aldec's Active-HDL. The library is listed as the "Xilinx ISE 13.2 unisim VHDL library."

 

Here is the exact IBUF.vhd file that was installed with 14.1. This machine never saw an installation of any other version of the Xilinx tools. Note the version number in the header. This file is identical to what was installed with Active-HDL.

 

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/IBUF.vhd,v 1.3 2009/08/22 00:26:02 harikr Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 11.1
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer
-- /___/   /\     Filename : IBUF.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/16/08 - Added IBUF_LOW_PWR attribute.
--    04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
-- End Revision

----- CELL IBUF                         -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

entity IBUF is
  generic(
    CAPACITANCE : string := "DONT_CARE";
    IBUF_DELAY_VALUE : string := "0";
    IBUF_LOW_PWR : boolean :=  TRUE;
    IFD_DELAY_VALUE  : string := "AUTO";
    IOSTANDARD  : string := "DEFAULT"
    );

  port(
    O : out std_ulogic;

    I : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    IBUF : entity is true;
end IBUF;

architecture IBUF_V of IBUF is
begin

  prcs_init : process
  variable FIRST_TIME        : boolean    := TRUE;
  begin
     
     If(FIRST_TIME = true) then
        if((CAPACITANCE = "LOW") or
           (CAPACITANCE = "NORMAL") or 
           (CAPACITANCE = "DONT_CARE")) then 
           FIRST_TIME := false;
        else  
           assert false
           report "Attribute Syntax Error: The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE"
           severity Failure;
        end if;

--  
        if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or
          (IBUF_DELAY_VALUE = "2")  or (IBUF_DELAY_VALUE = "3") or
          (IBUF_DELAY_VALUE = "4")  or (IBUF_DELAY_VALUE = "5") or
          (IBUF_DELAY_VALUE = "6")  or (IBUF_DELAY_VALUE = "7") or
          (IBUF_DELAY_VALUE = "8")  or (IBUF_DELAY_VALUE = "9") or
          (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or
          (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or
          (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or
          (IBUF_DELAY_VALUE = "16")) then
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. "
           severity Failure;
        end if;

--
        if((IBUF_LOW_PWR = TRUE) or
           (IBUF_LOW_PWR = FALSE)) then
           FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IBUF_LOW_PWR are TRUE or FALSE"
           severity Failure;
        end if;

--  
        if((IFD_DELAY_VALUE = "AUTO") or (IFD_DELAY_VALUE = "auto") or
          (IFD_DELAY_VALUE = "0")     or (IFD_DELAY_VALUE = "1") or
          (IFD_DELAY_VALUE = "2")     or (IFD_DELAY_VALUE = "3") or
          (IFD_DELAY_VALUE = "4")     or (IFD_DELAY_VALUE = "5") or
          (IFD_DELAY_VALUE = "6")     or (IFD_DELAY_VALUE = "7") or
          (IFD_DELAY_VALUE = "8")) then
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IFD_DELAY_VALUE are AUTO, 0, 1, ... , or 8"
           severity Failure;
        end if;

     end if;
     wait; 
  end process prcs_init;
    

  O <= TO_X01(I) after 0 ps;
end IBUF_V;

 

 

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Historian
Historian
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Registered: ‎02-25-2008

Re: Spartan 3A IBUFDS and IBUFGDS models and their delay generics

After further poking around, I've discovered that the Verilog libraries do not implement the delays either.

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Historian
Historian
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Registered: ‎02-25-2008

Re: Spartan 3A IBUFDS and IBUFGDS models and their delay generics

Webcase initial response:

 

"Your Xilinx Technical Support case has been dispatched to an FPGA Fabric specialist Product Applications Engineer (PAE) based on the keywords of your case."

 

No, it's not a fabric issue.

 

it's a simulation model problem.

 

Oy.

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Historian
Historian
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Registered: ‎02-25-2008

Re: Spartan 3A IBUFDS and IBUFGDS models and their delay generics


@gszakacs wrote:

What version of ISE are you using?  On ISE 13.4 I have a Spartan 3A design with variable delays and

these seem to be modeled correctly during behavioral simulation.  it uses the IBUF_DLY_ADJ primitive.

 

-- Gabor


Sorry, misread this.

 

I am not using the dynamic delay feature, which apparently does model the delay. I'm using the static delay, which has broken models.

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Professor
Professor
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Registered: ‎08-14-2007

Re: Spartan 3A IBUFDS and IBUFGDS models and their delay generics

It appears that the IBUF_DLY_ADJ and IBUFDS_DLY_ADJ do have the delays built into the

behavioral models.  As a workaround you could map your IBUF wih fixed delay to an IBUF_DLY_ADJ

with its select lines tied to a constant.  I have verified that this and the DELAY_OFFSET attribute

are both modeled.

 

-- Gabor

-- Gabor
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Historian
Historian
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Registered: ‎02-25-2008

Re: Spartan 3A IBUFDS and IBUFGDS models and their delay generics


@gszakacs wrote:

It appears that the IBUF_DLY_ADJ and IBUFDS_DLY_ADJ do have the delays built into the

behavioral models.  As a workaround you could map your IBUF wih fixed delay to an IBUF_DLY_ADJ

with its select lines tied to a constant.  I have verified that this and the DELAY_OFFSET attribute

are both modeled.

 

-- Gabor


... but that doesn't work when the output of the IBUF needs to connect to an IDDR2.

 

EDIT: the IFD_DELAY_VALUE can't be used when you use IDDR2 input flops. At least, that's what the mapper tells me.

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