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Newbie shirobon
Newbie
549 Views
Registered: ‎03-11-2018

Strange simulator behavior when using for loops

I'm using the simulator in Vivado to test one of my designs, and I'm getting some strange behavior.

 

I'm using a for loop using an integer i twice, the first time 256 times, and the second time 64 times.

However, the first loop, instead of incrementing i each time, it creates 256 other signals which are constant for the whole simulation, with the names "_fu_param(loop iteration)_37[31:0]."

During this time the i integer is undefined (since it isn't set before the for loop, but should be set upon the for loop) as seen from the simulation.

This leads me to believe for some reason the first for loop isn't executing as it should.

 

On the 2nd loop which uses i, it gets incremented as expected. (slightly after 6us). So now i is defined, and no extra signals are generated.

 

I'm pretty confused why, since the code for both loops in regards to the for loop statement are the same, the first just stops at 255 and the second stops at 63, so I don't know why the first loop is just generated 256 signals instead of updating i.

 

Simulation:

sim.PNG

 

Code:

`timescale 1ns / 1ps

module ControlToMemory_tb();
    reg CLK, RST, CE, WR;
    reg[7:0] Data;
    wire POLL;
    
    reg[5:0] Index[0:3];
    wire[5:0] Waveform[0:3];
    
    wire[5:0] WavetableSample;
    wire[7:0] WavetableAddress;
    wire WavetableWE;
    
    integer i;
    
    ControlUnit C1(CLK, RST, CE, WR, Data, POLL, WavetableSample, WavetableAddress, WavetableWE);
    
    WavetableRAM W1(CLK, WavetableWE, WavetableAddress, {Index[0], Index[1], Index[2], Index[3]}, 
                    WavetableSample, Waveform[0], Waveform[1], Waveform[2], Waveform[3]);    
                      
    always begin
        #1 CLK = ~CLK;
    end
    
    initial begin
        CLK <= 1'b0;
        RST <= 1'b0;
        CE <= 1'b0;
        WR <= 1'b0;
        Data <= 8'b00000000;
        #1;
        RST <= 1'b1;
        #4;
        
        //write memory
        for(i = 0; i < 256; i = i+1) begin
            CE <= 1'b1; //enable chip
            #4;
            WR <= 1'b1;
            Data <= {2'b10, i[5:0]};
            #4;
            WR <= 1'b0; //commit
            #4;
            WR <= 1'b1; //new byte
            Data <= i[7:0];
            #4;
            WR <= 1'b0; //commit
            #4;
            CE <= 1'b0;
            #4;
        end
        
        //read back each memory bank
        for(i = 0; i < 64; i = i+1) begin
            Index[0] <= i;
            Index[1] <= i;
            Index[2] <= i;
            Index[3] <= i;
            #4;
        end
        
        #10 $finish;
    end
endmodule
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1 Reply
Xilinx Employee
Xilinx Employee
501 Views
Registered: ‎09-25-2014

Re: Strange simulator behavior when using for loops

Hi @shirobon,

 

This is a bug in the simulator. This is seen only when you use part select of the loop variable. Hence you were seeing this issue in the first loop only. I have reported it to the factory.

 

Thanks,

Srimayee