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Newbie
Newbie
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Registered: ‎05-30-2020

Strange timing of the simulation run

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When I execute a command to run simulation for 1 second, Vivado runs it for 10 seconds instead (by the time shown in the simulation timeline window). Any ideas why this may be happening?

PS v2019.2.1

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Strange timing of the simulation run

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Indeed, it should be a tool issue. Thanks for reporting this. I'll file a CR to have it fixed.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Strange timing of the simulation run

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I haven't seen such issue before. Did you type "run 1s" command in Tcl after simulation is launched? Can you attach a test case to reproduce it?

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Contributor
Contributor
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Registered: ‎11-16-2017

回复: Strange timing of the simulation run

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I used the toolbar button in the simulator GUI. Also, I found out that this problem doesn't happen in v2019.1.3, so apparently it's a new bug in 2019.2.1

It's happening in all the projects for me, no special test project is needed.

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Voyager
Voyager
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Registered: ‎06-20-2012

回复: Strange timing of the simulation run

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@graces 

I confirm.

Just test:

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;

entity lab6_tb is
end lab6_tb;
architecture arch of lab6_tb is
signal clk_tb : std_logic;
begin
clk_process: process
begin
    clk_tb <= '0';
    wait for 500 ns;
    clk_tb <= '1';
    wait for 500 ns;
end process;
end architecture ;

command "run 1 s" run for 10 second and "run 2 s"   run for 20 second.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Strange timing of the simulation run

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Indeed, it should be a tool issue. Thanks for reporting this. I'll file a CR to have it fixed.

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