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Adventurer
Adventurer
8,676 Views
Registered: ‎02-11-2014

Structural model- Memory design using D-Flipflop

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Hi,

In my project, I am designing a 8bit registers using D-Flipflop. During simulation when I give D=1, and CLK=1, I was able to get output. But when I give a continious Clock input as shown in below provided test bench ,I am not getting any output. Below provide is the verilog code for D-Flipflop,MUx and D-flipFlop test bench. Mux is used to provide a stable input to Flipfllop.

Please help, I couldnt find out where I didmistake

 

module D_flipflop(output Q2,input Data,CLK,S
);
wire Q2;
wire x0,a0,a1,a2;
wire xx0,aa0,aa1,aa2;
wire CLK_not;
wire x1,x2;


nand nand1 (a0,Data1,CLK);
nand nand2 (a1,x0,CLK);
nand nand3 (Q2,a0,a2);
nand nand4 (a2,a1,Q2);

 

Mux_2to1 MUX1(Data1,Data,Q2,S);


endmodule

 

module Mux_2to1(mux_out,input0,input1,S
);
input input0,input1,S;
output mux_out;
wire s_,x1,x2;
not (s_,S);
and and1(x1,s_,input0);
and and2(x2,S,input1);
or (mux_out,x1,x2);
endmodule

 

//// D-FLIPFLOP TEST BENCH/////

module D_Flipfloptest;

// Inputs
reg Data;
reg CLK;
reg S;

// Outputs
wire Q2;

// Instantiate the Unit Under Test (UUT)
D_flipflop uut (
.Q2(Q2),
.Data(Data),
.CLK(CLK),
.S(S)
);

initial begin
// Initialize Inputs
Data = 0;
CLK = 0;
S = 0;


#5 Data=1;
#5 forever CLK=~CLK;

#5 $display("%b",Q2);

end

endmodule

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1 Solution

Accepted Solutions
Adventurer
Adventurer
12,625 Views
Registered: ‎02-11-2014

Re: Structural model- Memory design using D-Flipflop

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I found out the error. I didntprovide propoer delay in testbench.

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3 Replies
Adventurer
Adventurer
12,626 Views
Registered: ‎02-11-2014

Re: Structural model- Memory design using D-Flipflop

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I found out the error. I didntprovide propoer delay in testbench.

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Instructor
Instructor
8,653 Views
Registered: ‎08-14-2007

Re: Structural model- Memory design using D-Flipflop

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I see at least two issues in the testbench:

 

initial begin
   // Initialize Inputs
  Data = 0;
  CLK = 0;
  S = 0;


  #5 Data=1;
  #5 forever CLK=~CLK;

  #5 $display("%b",Q2);

end

 

1) The red line means "wait 5 time units, then constantly toggle CLK with no time delay"

That's like an infinite clock frequency, and would preven the simulation from advancing in time.

 

I assume you meant something like:

 

forever #5 CLK = ~CLK;

 

This means "constantly wait 5 time units then toggle CLK" which would give a clock period of 10 time units with the first edge occurring after 5 time units.

 

2) The green line is after the forever loop.  It will never get executed.

-- Gabor
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Adventurer
Adventurer
8,626 Views
Registered: ‎02-11-2014

Re: Structural model- Memory design using D-Flipflop

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Hi Gabor,

Thanks and you were right. 

 

As i mentioned I am trying to create an "8 bit register file using structural model"module. When I tested my register file sepreatly, it is working fine. However, when I call this file in main program it give incorrect result, even if the input given is correct. What may be the issue? 

 

thanks

 

kathy

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