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Visitor xsilverx
Visitor
277 Views
Registered: ‎11-19-2012

Sub-module simulation in Vivado

Hi! I tried to simulate a sub-module from my project's bd in Vivado 2018.4. I followed these instructions

https://www.xilinx.com/support/answers/60703.html

But instantiation didn't work.sim_submodule_1.pngFailed instantiation

What should I try to make instantiation correct in TB?

Could it be caused by my simulation sources list?ss_mine.pngSimulation sources for sub-module tb

 

ss_top.pngSimulation sources for top-level tb

 

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3 Replies
Xilinx Employee
Xilinx Employee
235 Views
Registered: ‎07-16-2008

回复: Sub-module simulation in Vivado

Did you switch to manual compile order as suggested in the AR?

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Visitor xsilverx
Visitor
225 Views
Registered: ‎11-19-2012

回复: Sub-module simulation in Vivado


@graces wrote:

Did you switch to manual compile order as suggested in the AR?


I have tried to set it but:

1. When I set manual compile order for simulation there is message: Module references are out-of-date. Refresh Changed Modules. And if I choose Refresh... It causes a lot of errors.

2. When I run simulation there were a lot of errors in the other TBs (they are ok before it). Simulation did not run.

Finally I start it:

1. I don't Refresh Changed Modules.

2. I delete all other TBs from project.

Is it a correct actions or I should try to avoid it?

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Xilinx Employee
Xilinx Employee
217 Views
Registered: ‎07-16-2008

回复: Sub-module simulation in Vivado

As I see it, if you set the sub-module testbench to top, it shouldn't affect other TB hierarchies.

Would you please provide the project archive so that I can try at my end?

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