10-07-2018 07:15 PM
I am getting syntax errors near both dflipflop 's and I don't know why. Could someone help me.
module REG #(parameter N=8)
(input clk, en, in,
wire [N-1:0] sum;
always @* begin
dflipflop ff[N-1:0](.d(in), .clk(clk), .q(sum));
dflipflop ff[N-1:0](.d(0), .clk(clk), .q(sum));
mux2 #(.N(N)) mu(.in0(sum), .in1(0), .sel(en), .out(sum));
10-07-2018 08:27 PM
The range specification in module instantiation is supported in system verilog.
You need to compile the file in system verilog mode.
xvlog -sv reg.v
In project mode, select the file and change the Type from Verilog to SystemVerilog in Source File Properties window, and then launch simulation.
10-08-2018 11:36 AM
@graces -No, the range specification of module instantiation was in the original verilog-1995 spec and worked fine in Verilog-XL - so that's not the trouble here.
@graysonsmith - your trouble is you're trying to instantiate a module WITHIN a procedural block. That's not allowed. Move the dflipflop instantiation outside the procedural block, and you should be good to go.