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Visitor graysonsmith
Visitor
382 Views
Registered: ‎09-23-2018

Syntax errors near dflipflop

I am getting syntax errors near both dflipflop 's and I don't know why. Could someone help me.

```

module REG #(parameter N=8)
(input clk, en, in,
input out);

wire [N-1:0] sum;
always @* begin
case(en)
1'b1:
begin
dflipflop ff[N-1:0](.d(in), .clk(clk), .q(sum));
end
1'b0:
begin
dflipflop ff[N-1:0](.d(0), .clk(clk), .q(sum));
end
endcase
end
mux2 #(.N(N)) mu(.in0(sum), .in1(0), .sel(en), .out(sum));
endmodule

```

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2 Replies
Xilinx Employee
Xilinx Employee
363 Views
Registered: ‎07-16-2008

回复: Syntax errors near dflipflop

The range specification in module instantiation is supported in system verilog.

You need to compile the file in system verilog mode.

xvlog -sv reg.v

 

In project mode, select the file and change the Type from Verilog to SystemVerilog in Source File Properties window, and then launch simulation.

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Scholar markcurry
Scholar
337 Views
Registered: ‎09-16-2009

回复: Syntax errors near dflipflop

@graces -No, the range specification of module instantiation was in the original verilog-1995 spec and worked fine in Verilog-XL - so that's not the trouble here.

 

@graysonsmith - your trouble is you're trying to instantiate a module WITHIN a procedural block.  That's not allowed.  Move the dflipflop instantiation outside the procedural block, and you should be good to go.

 

Regards,

 

Mark

 

 

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