cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
26,971 Views
Registered: ‎05-21-2009

Synthesis of floating point in VHDL

Jump to solution

Hi guys,

 

I have a couple of queries regarding floating-point in VHDL and how it is synthesized. It is my understanding that VHDL2008 and up supports data type FLOAT. I've used this data type to implement a controller in VHDL, but I am struggeling a lot. The implementation does not want to simulate in Questasim 10. I keep getting an error: "Fatal error in Subprogram to_float at C:/questasim_10.1/win32/../vhdl_src/ieee/float_generic_pkg-body.vhdl line 2855". I have the float_pkg included.

 

This raised some questions that I hope someone can answer. How is FLOAT synthesized/interpreted by the synthesizer? From the error message above, you will see that the issue lies with the TO_FLOAT function. This happens when I try to convert a STD_LOGIC_VECTOR signal to FLOAT in real time. However, when I use TO_FLOAT to convert CONSTANTS to FLOAT, this function works fine. I'm assuming this has something to do with the synthesis of FLOAT. Can someone please explain?

 

Thanks in advance

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Instructor
Instructor
37,915 Views
Registered: ‎07-21-2009

Re: Synthesis of floating point in VHDL

Jump to solution

So, if I understand you correctly, just by using the float library doesn't allow the compiler to infer a FLOAT data path.

 

That is correct.

 

Are you implying that in order to multiply, add and subtract (the typical operations in my implementation), I have to add Xilinx IP floating-point IP cores for each operation?

 

A floating point datapath is like any other logic circuit which must be instantiated.  If you design the datapath to handle mult, add, and sub -- that is what you should expect.  Or you can add an embedded processor and implement FP arithmetic in software/firmware routines.  Xilinx and Xilinx partners offer FP IP cores.  I'm sure there are freeware FP math cores to be found at opencores.org.

 

What does a self-designed data path entail?

 

FP math is generally quite complex compared to integer math.  If your needs are complex, the implementation (and debugging and verification) can take months.  It is easy to get bogged down in the details of the corner cases -- the unusual combinations of operands which produce unusual results -- and the various possible implementations of rounding modes.

 

You have made a common mistake.  There is an abundance of information in these forums and on the web about FP arithmetic and hardware implementations.

 

If you can avoid using FP arithmetic -- using integer or fixed point arithmetic instead (also called "block floating point") -- you will likely save yourself much time and a considerable amount of FPGA resources.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

0 Kudos
11 Replies
Highlighted
Xilinx Employee
Xilinx Employee
26,960 Views
Registered: ‎05-14-2008

Re: Synthesis of floating point in VHDL

Jump to solution

I think you should post this in the user forums of Modelsim since you're encountering Questasim error when running simulation. However, I'll move your post to the "Simulation and Verification" board.

 

Vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Explorer
Explorer
26,954 Views
Registered: ‎05-21-2009

Re: Synthesis of floating point in VHDL

Jump to solution
Hi Vivian, So you think it is more of a simulation issue than a synthesis one? Thanks for moving my post.
0 Kudos
Highlighted
Instructor
Instructor
26,950 Views
Registered: ‎07-21-2009

Re: Synthesis of floating point in VHDL

Jump to solution

Hi Vivian, So you think it is more of a simulation issue than a synthesis one?

 

I can guarantee you that using a VHDL floating point library does NOT auto-magically create a floating point data path which is synthesised to hardware.  That's not how floating point processor hardware is built.

 

A hardware floating point data path must be designed and implemented in your source code, either "from scratch" or by using a (usually licensed) core.  If you haven't explicitly defined hardware for floating point arithmetic, it isn't in the synthesised hardware.

 

Does this make sense to you?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Explorer
Explorer
26,946 Views
Registered: ‎05-21-2009

Re: Synthesis of floating point in VHDL

Jump to solution
Hi Bob, I think I understand, but could you please ellaborate a bit more? Let me give a short summary of my implementation: I have a STD_LOGIC_VECTOR signal coming from a different module. I want to convert this signal to FLOAT because I have a couple of contants (also converted to FLOAT) I want to multiply this signal with. The result is saved inside an array and I'm using the different values in the array to do FLOAT addition and subtraction. So, if I understand you correctly, just by using the float library doesn't allow the compiler to infer a FLOAT data path. This will clarify the issue I'm having with the TO_FLOAT function in real time. You said that to use floating-point I have to design a data flow from scratch or use an IP core. Are you implying that in order to multiply, add and subtract (the typical operations in my implementation), I have to add Xilinx IP floating-point IP cores for each operation? What does a self-designed data path entail?
0 Kudos
Highlighted
Instructor
Instructor
37,916 Views
Registered: ‎07-21-2009

Re: Synthesis of floating point in VHDL

Jump to solution

So, if I understand you correctly, just by using the float library doesn't allow the compiler to infer a FLOAT data path.

 

That is correct.

 

Are you implying that in order to multiply, add and subtract (the typical operations in my implementation), I have to add Xilinx IP floating-point IP cores for each operation?

 

A floating point datapath is like any other logic circuit which must be instantiated.  If you design the datapath to handle mult, add, and sub -- that is what you should expect.  Or you can add an embedded processor and implement FP arithmetic in software/firmware routines.  Xilinx and Xilinx partners offer FP IP cores.  I'm sure there are freeware FP math cores to be found at opencores.org.

 

What does a self-designed data path entail?

 

FP math is generally quite complex compared to integer math.  If your needs are complex, the implementation (and debugging and verification) can take months.  It is easy to get bogged down in the details of the corner cases -- the unusual combinations of operands which produce unusual results -- and the various possible implementations of rounding modes.

 

You have made a common mistake.  There is an abundance of information in these forums and on the web about FP arithmetic and hardware implementations.

 

If you can avoid using FP arithmetic -- using integer or fixed point arithmetic instead (also called "block floating point") -- you will likely save yourself much time and a considerable amount of FPGA resources.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

0 Kudos
Highlighted
Explorer
Explorer
26,940 Views
Registered: ‎05-21-2009

Re: Synthesis of floating point in VHDL

Jump to solution

Thank you very much Bob, you have been a great help. This is the first time I'm trying to use FP on an FPGA. Its been a while since last programming in VHDL and I've only recently discovered that I can use FP in VHDL. I read through the FP user guide available online, but I was unsure on how FP is synthesized. I was hoping that the FP data path can just be inferred.

 

You mentioned fixed-point arithmetic. Using type FIXED (SFIXED or UFIXED), will the fixed-point data path be inferred? I know that you can specify the number of bits used before and after the decimal point. Can I use this format throughout my implementation to multiply, add and subtract, or should I treat the integer and decimal parts separately?

0 Kudos
Highlighted
Instructor
Instructor
26,937 Views
Registered: ‎07-21-2009

Re: Synthesis of floating point in VHDL

Jump to solution

There are others in these forums who are VHDL wizards.  I took the cheap expedient path, pursuing Verilog.  So I cannot answer your questions on casting variable types in VHDL.

 

When I design fixed-point arithmetic logic, I either sort out the required precision and radix point position on paper, or I use a spreadsheet to simulate my algorithms for range and bounds.  Make sure you document you code well with comments, they will prove valuable for debugging and maintenance of your code.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Teacher
Teacher
26,933 Views
Registered: ‎09-09-2010

Re: Synthesis of floating point in VHDL

Jump to solution
Have you read the documentation for the VHDL 'float' type yet?
http://www.vhdl.org/fphdl/Float_ug.pdf

As Bob suggests, whether you can simulate it or not, the current versions of XST will not synthesize it.

For non-synthesizale models, I use 'real' types, but fortunately I don't need to synthesize non-integer arithmetic types.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos
Explorer
Explorer
26,930 Views
Registered: ‎05-21-2009

Re: Synthesis of floating point in VHDL

Jump to solution
Thanks for the link rcingham. Yes, I've read the documentation. However, I'm under the impression that float is synthesizable and the implementation should be designed for floating-point. Am I still missing something?
0 Kudos
Highlighted
Teacher
Teacher
7,929 Views
Registered: ‎09-09-2010

Re: Synthesis of floating point in VHDL

Jump to solution
Type float is synthesizeable only if the synthesis tools support it.
XST does not yet support it (as far as I am aware).

If anybody KNOWS differently, please speak up...

------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos
Highlighted
Instructor
Instructor
7,927 Views
Registered: ‎07-21-2009

Re: Synthesis of floating point in VHDL

Jump to solution

Type float is synthesizeable only if the synthesis tools support it.
XST does not yet support it (as far as I am aware).

If anybody KNOWS differently, please speak up...

 

XST will not design a floating point arithmetic datapath for you, if that is what is being asked.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos