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Scholar samcossais
Scholar
12,140 Views
Registered: ‎12-07-2009

System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

Hi

I am working on a system containing both Spartan-6 LXT and Kintex-7. I am using Vivado 2013.3 and Modelsim SE 10.3 64b. I would like to know how we can simulate both FPGAs in a unique environment using Xilinx libraries. How are we supposed to set the libraries ?

 

For the Spartan-6 LXT components models, I get this type of error :

ERROR : The following component GTPA1_DUAL at instance sim_top.tbench_top.sim_host_srio_core_xt_wrap.rio_de_wrapper.phy_wrapper.srio_gt_wrapper.gtp_wrapper_i.tile0_gtp_wrapper_i.gtpa1_dual_i is not supported for retargeting in this architecture.  Please modify your source code to use supported primitives.

 

I am NOT going to modify my sources because the model isn't provided in Vivado simulation libraries... I obviously need to make my Spartan-6 work.

 

In my new project though, the Spartan-6 libraries seem to not be found in the simulation libraries produced through the Vivado compile_simlib command.

 

I made the libraries using the following command :

compile_simlib        -directory C:/Xilinx/Vivado/2013.3/sim_lib/                             \
-family kintex7        -family artix7        -language vhdl        -language verilog         \
-library unisim        -library xilinxcorelib    -library simprim                                       \
-simulator modelsim        -simulator_exec_path C:/modeltech64_10.3/win64

 

and added the following lines to my Modelsim project file (I don't use the VHDL libraries for the moment) :
    unisims_ver        = C:\Xilinx\Vivado\2013.3\sim_lib\unisims_ver
    xilinxcorelib_ver  = C:\Xilinx\Vivado\2013.3\sim_lib\xilinxcorelib_ver
    secureip              = C:\Xilinx\Vivado\2013.3\sim_lib\secureip
    simprims_ver     = C:\Xilinx\Vivado\2013.3\sim_lib\simprims_ver

 

With these libraries the Spartan-6 primitives (such as the GTPA1_DUAL above) are not recognized and return errors.

With both Spartan-6 and Kintex-7 in the same simulation, are we supposed to use the ISE 14.7 libraries and add if necessary the new models from the Vivado libraries to our project manually ?

 

Regards, Sam

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16 Replies
Scholar samcossais
Scholar
12,135 Views
Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

I tried to use the ISE 14.7 libraries instead of the Vivado 2013 but I got this type of errors when loading vsim :

 

** Error: (vopt-2732) Module parameter 'IS_CLKINSEL_INVERTED' not found for override at vivado13_prj_rx0.srcs/sources_1/ip/rx0_mmcm_main/rx0_mmcm_main_funcsim.v(171).

 

I did not get this error when I used the Vivado libraries. So I have basically no good solution for my problem. Either I use Vivado libraries and I get errors on Spartan-6 primitives, or I use ISE libraries and I get errors on the new Kintex-7 primitives.

 

One solution would be to have both libraries but the names for the primitives are the same, but work differently depending on the version. The worst is the empty modules for the unsupported Spartan-6 libraries. I can understand they will not be supported with Vivado tools, but then why put an empty file ? It's just a disturbance as it may be used instead of a separate library you might add for Spartan-6 compliance.

 

I don't think I am the only one that needs to simulate a system with both 6 and 7 series FPGAs, while using Vivado for the 7 series IPs and implementation.

 

For now it doesn't seem to be well handled at all.

Or is there something I misunderstood ?

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Scholar samcossais
Scholar
12,130 Views
Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

Is it correct to consider that we basically need to add primitive models (for instance the above GTPA1_DUAL primitive) manually ?

 

Therefore we may make mistakes when choosing which file use, with also the risk of version conflicts and it will be much harder to manage library updates etc...

 

Normally this should be transparent and I think it's a serious concern for simulation purpose.

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Xilinx Employee
Xilinx Employee
12,113 Views
Registered: ‎07-31-2012

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

Hi,

 

To use the GT models, you need the secure IP libraries. You need to compile your Xilinx libraries for modelsim using the compxlib tool. More details on how to run compxlib can be found from the link - http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/sim.pdf Pg 112.

 

More information and command line for how to run compxlib can be found from the link Pg 323 - http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/devref.pdf

 

eg: compxlib -s mti_se -arch kintex7 -l verilog -lib all

 

The -lib is used for specifying whether it is unisim, simprim, secure ip etc. 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Scholar samcossais
Scholar
12,107 Views
Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

Anirudh

Do you basically tell me to use the ISE 14.7 libraries ? If you read well my second post, I already tried with ISE 14.7 simulation libraries:


@samcossais wrote:

Alright, I tried to use the ISE 14.7 libraries instead of the Vivado 2013 but I got this type of errors when loading vsim :

 

** Error: (vopt-2732) Module parameter 'IS_CLKINSEL_INVERTED' not found for override at vivado13_prj_rx0.srcs/sources_1/ip/rx0_mmcm_main/rx0_mmcm_main_funcsim.v(171).


I made them using the ISE Simulation Libraries Compilation Wizard but it has worked for me for the last 5 years so I guess it still does (I did use compxlib too a long time ago). I don't use the EDK libraries so I didn't compile "-all" the libraries. Here are the one I used when I tested with ISE libraries :

   secureip                = C:\Xilinx\14.7\ISE_DS\ISE\verilog\mti_se\10.1b\nt64\secureip
   simprims_ver      = C:\Xilinx\14.7\ISE_DS\ISE\verilog\mti_se\10.1b\nt64\simprims_ver
   xilinxcorelib_ver   = C:\Xilinx\14.7\ISE_DS\ISE\verilog\mti_se\10.1b\nt64\xilinxcorelib_ver
   unisims_ver         = C:\Xilinx\14.7\ISE_DS\ISE\verilog\mti_se\10.1b\nt64\unisims_ver

 

As I said, if I use the ISE libraries, I get multiple errors with Kintex primitives, and if I use the new Vivado libraries, the Spartan-6 primitives are not supported.

 

If there is something I did wrong, tell me how to correct it please.

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Xilinx Employee
Xilinx Employee
12,099 Views
Registered: ‎07-31-2012

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

Hi,

 

ISE or Vivadosimulation libraries, it should not make a difference.

 

However please check your compilation log in case you havent observed it to see if there were any warnings. That should give you a clue on what went wrong in the compilation.

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Scholar samcossais
Scholar
12,096 Views
Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?


@athandr wrote:

Hi,

 

ISE or Vivadosimulation libraries, it should not make a difference.

 

However please check your compilation log in case you havent observed it to see if there were any warnings. That should give you a clue on what went wrong in the compilation.

 


If you read all my posts here, you should notice it did make a difference. I already posted the error logs. As the problem comes from version conflicting / unsupported libraries, these errors only occurs when loading vsim, not at compile.

 

Edit : Neither ISE14.7 compxlib nor Vivado 2013.3 compile_simlib generate any error or warning.

 

Edit2 : The main difference between compiling simulation libraries with Vivado 2013.3 compile_simlib and ISE14.7 compxlib is the -family switch. With Vivado 2013.3 you do no have the spartan6 option. This is my problem.

 

Edit3: As I made the library a few months ago, I just checked my compxlib log in case I forgot to include Kintex-7 :

compxlib -s mti_se -64bit -p C:\modeltech64_10.1b\win64 -l verilog -arch artix7 -arch kintex7 -arch spartan6 -arch virtex6 -arch virtex7 -arch zynq -lib unisim -lib xilinxcorelib -lib simprim -w -verbose
I had one (insignificant) warning but it is for the FIR IP and I don't use it.

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Scholar samcossais
Scholar
12,039 Views
Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

I was able to make the simulation load by executing the following vlog commands in order to compile the Spartan-6 GTP models from the ISE sources into the Vivado library :

 

vlog    -work unisims_ver -O5 +nospecify +notimingchecks \
C:/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/GTPA1_DUAL.v

 

vlog    -work secureip -O5 +nospecify +notimingchecks \
C:/Xilinx/14.7/ISE_DS/ISE/secureip/mti/gtpa1_dual_mti/gtpa1_dual_001.vp \
C:/Xilinx/14.7/ISE_DS/ISE/secureip/mti/gtpa1_dual_mti/gtpa1_dual_002.vp

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Scholar samcossais
Scholar
12,038 Views
Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

For now I am still not simulating my whole system with the Spartan-6, and I replaced the testbench side host SRIO core for Spartan-6 by one for Kintex-7 (SRIO Gen2 v3.0) so I don't need the Spartan-6 libraries in a hurry.

 

However I cannot consider this problem as solved as I don't know if adding "old" ISE models for Spartan-6 one by one manually to the new Vivado libraries will work / be a satisfying solution for models other than GTP.

 

What does Xilinx recommend for mixed architecture simulation ? Is there a better solution ?

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Scholar samcossais
Scholar
11,969 Views
Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

I assume the use of a confguration file such as the one I mentionned here :

http://forums.xilinx.com/t5/Simulation-and-Verification/SRIO-Gen2-netlist-models-slow-behavioral-models-encrypted/m-p/435162#M9342

should make it possible to mix a Kintex-7 and a Spartan-6 in my simulation.

 

I think I will map my libraries this way :


unisims_ver = C:\Xilinx\Vivado\2013.3\sim_lib\unisims_ver

ise_unisims_ver = C:\Xilinx\14.7\ISE_DS\ISE\verilog\mti_se\10.3\nt64\unisims_ver

etc.


 

 

and set the highest priority to Vivado libraries :


config cfg_sim_top;


    design work.sim_top;


    default liblist fifo_generator_v11_0 fifo_generator_v10_0 dist_mem_gen_v8_0 blk_mem_gen_v8_0

    srio_gen2_v3_0
    unisims_ver secureip xilinxcorelib_ver ise_unisims_ver ise_secureip ise_xilinxcorelib_ver;

 

endconfig


 

 

I think I will use the keyword instance to set exceptions for the Spartan-6 (fpga2) for any unsupported model I may find.

 

But I actually did not find a lot of help on how to use config.

 

Does for example :

instance sim_top.fpga2_top use ise_unisims_ver.DSP48E1;

works for all the instances below fpga2_top (that is the whole Spartan-6 FPGA) ?

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Moderator
Moderator
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Registered: ‎04-17-2011

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

Ok, so Vivado libraries are located in:
C:\Xilinx\Vivado\2013.4\data\verilog\src
C:\Xilinx\Vivado\2013.4\data\vhdl\src
These would contain only 7-series primitives.
So, compile_simlib would compile only these files and add it in modelsim.ini file. So, you Kintex-7 is taken care of.

Now coming to Spartan-6 which is part of ISE libraries, these are present at location:
C:\Xilinx\Vivado\2013.4\ids_lite\ISE\verilog\src
C:\Xilinx\Vivado\2013.4\ids_lite\ISE\vhdl\src
under the set of libraries unisims, simprims etc.
So, you need to point to this location in your modelsim script using -y switch ( -y <path> Specify Verilog source library directory) in vlog.
Regards,
Debraj
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Scholar samcossais
Scholar
9,139 Views
Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

I don't want to be rude but, is there anyone that can read my posts here and actually reply to the questions inside ?

 

I mentionned multiple times that I want to know how we are supposed to deal with the version conflicts between 7-series primitives and 6-series primitives in simulation.

 

For example in the libraries you mentionned :

C:\Xilinx\Vivado\2013.4\data\verilog\src\DSP48E1

and

C:\Xilinx\Vivado\2013.4\ids_lite\ISE\verilog\src\DSP48E1

have the same name but are quite different. As the 7-series version has 6 additional parameters, it WILL GENERATE ERRORS in either the 6-series instance or the 7-series instance when mixed in the same sim. environment.

 

I finally found out (with the help of Xilinx documentation) that some advanced settings (e.g. set a simulation config file in verilog) should let me do this mixed architecture simulation.

 

In that regard UG900 was of good help, but it did not say how to actually load the simulation with the config (I found out myself) nor how to specify a primitive model for one top file and all the instances below (as I asked in my last post).

 

This is basically my only remaining question, unless you have remarks about my multiple previous posts in this topic, which would be greatly appreciated.

 

Now to be entirely honest, I have 10 years of experience in FPGA development, including developing simulation testbench, and I am not a huge fan of the simulation libraries in Vivado (and the way mixed FPGA series are dealt with)..

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

My suggestion would be to to compile Vivado simulation libraries (kintex-7) using compile_simlib and then to manually compile the specific S6 components you are using. This should be a significantly smaller subset. You should be able to just compile it directly for each component you want to use..

You can also compile it into the work library if you want too, just treat this as any other user module.

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Scholar samcossais
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Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?


@graces wrote:

My suggestion would be to to compile Vivado simulation libraries (kintex-7) using compile_simlib and then to manually compile the specific S6 components you are using. This should be a significantly smaller subset. You should be able to just compile it directly for each component you want to use..

You can also compile it into the work library if you want too, just treat this as any other user module.


That's what I mentionned in one of my first posts in this topic . I assume it works for primitive models indeed.

 

Also, in my case I am using a Spartan-6 so it is still ok, but what if I used a Virtex-6 and a Kintex-7 ? As I said in my previous post, the primitive DSP48E1 which is common to both Virtex-6 and Kintex-7 has a different number of parameters in Vivado and ISE. Same for MMCM. When using the DSP Macro or Clocking Wizard (which I've been using for a while), it will then generate errors if both FPGAs are simulated in the same environment. Hence my last question / remark about setting exceptions with a Verilog config file (I don't work in VHDL but I assume it is dealt with more easily as VHDL has built-in library management).

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?


@samcossais wrote:

I assume the use of a confguration file such as the one I mentionned here :

http://forums.xilinx.com/t5/Simulation-and-Verification/SRIO-Gen2-netlist-models-slow-behavioral-models-encrypted/m-p/435162#M9342

should make it possible to mix a Kintex-7 and a Spartan-6 in my simulation.

 

I think I will map my libraries this way :


unisims_ver = C:\Xilinx\Vivado\2013.3\sim_lib\unisims_ver

ise_unisims_ver = C:\Xilinx\14.7\ISE_DS\ISE\verilog\mti_se\10.3\nt64\unisims_ver

etc.


 

 

and set the highest priority to Vivado libraries :


config cfg_sim_top;


    design work.sim_top;


    default liblist fifo_generator_v11_0 fifo_generator_v10_0 dist_mem_gen_v8_0 blk_mem_gen_v8_0

    srio_gen2_v3_0
    unisims_ver secureip xilinxcorelib_ver ise_unisims_ver ise_secureip ise_xilinxcorelib_ver;

 

endconfig


 

 

I think I will use the keyword instance to set exceptions for the Spartan-6 (fpga2) for any unsupported model I may find.

 

But I actually did not find a lot of help on how to use config.

 

Does for example :

instance sim_top.fpga2_top use ise_unisims_ver.DSP48E1;

works for all the instances below fpga2_top (that is the whole Spartan-6 FPGA) ?


With regards to the Verilog configurations, here's the syntax statement in Verilog LRM.

 

config_declaration ::= (From Annex A -A.1.2)
config config_identifier ;
design_statement
{config_rule_statement}
endconfig
design_statement ::=
design { [library_identifier.]cell_identifier } ;
config_rule_statement ::=
default_clause liblist_clause
| inst_clause liblist_clause
| inst_clause use_clause
| cell_clause liblist_clause
| cell_clause use_clause

 

The instance clause is used to specify the specific instance to which the expansion clause shall apply.

 

As I understand it, the configuration rule applies to the current instance (subsections not included) when instance clause is used.

 

Another way I can think is to rename the V6 primitives in both the library (unisims_ver) source files and design files,

e.g. DSP48E1 to DSP48E1_V6

recompile the modified V6 libraries so that there's no name contention. 

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Scholar samcossais
Scholar
9,094 Views
Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

Thank you for your reply.

The problem is that if I edit the DSP48E1 source and change the name to DSP48E1_V6 it means I'll need to edit the upper source which is the coregen DSP Macro ( this is an example, not my case here because I use a Spartan-6 but the same can be said for other primitives). The sources for this 6-series FPGA are reused from a previous project so I would rather not edit its sources too much.

 

Now I don't have that many primitives for this FPGA so I think the instance keyword (in config file) should be enough, even if I need to repeat the code for all the primitive instances having compatibility issues.

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Scholar samcossais
Scholar
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Registered: ‎12-07-2009

Re: System containing a Spartan-6 and a Kintex-7. What Modelsim sim libraries ?

To sum up, here is the solution I propose (for Verilog) :

 

1 - Map my libraries this way :


unisims_ver = C:\Xilinx\Vivado\2013.3\sim_lib\unisims_ver

ise_unisims_ver = C:\Xilinx\14.7\ISE_DS\ISE\verilog\mti_se\10.3\nt64\unisims_ver

etc.


 

 

2- Create a configuration file (in my case cfg_sim_top.v)


config cfg_sim_top;


    design work.sim_top;


    default liblist fifo_generator_v11_0 fifo_generator_v10_0 dist_mem_gen_v8_0 blk_mem_gen_v8_0

    srio_gen2_v3_0
    unisims_ver secureip xilinxcorelib_ver ise_unisims_ver ise_secureip ise_xilinxcorelib_ver;

 

    instance sim_top.fpga2_top.example_module.dsp_macro0.DSP48E1 use ise_unisims_ver.DSP48E1;

[etc...]

 

endconfig


*this is an example for a Virtex-6 (DSP48E1) but it works the same way for a Spartan-6

 

3- load simulation with :


vsim  -L fifo_generator_v11_0 -L dist_mem_gen_v8_0 -L blk_mem_gen_v8_0 \

           -L unisims_ver -L secureip -L ise_xilinxcorelib_ver -L ise_unisims_ver work.cfg_sim_top work.glbl


 

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