System generator black box sim bug, has hardcoded path!

[dima2882]

Hello,

I've got a Vivado 2016.4 block diagram containing custom logic as well as a FIR Compiler 7.2 block. I generated output products for it and wanted to simulate it as a black box in System Generator. It failed, and the elaboration log spat out a Xilinx hardocded path that screwed everything up. Here is the contents of elaborate.log:

Vivado Simulator 2016.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto 4ed16aa075984127a4da5573e297555a --debug off --dll --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot Reloadable_FIR_Top_wrapper_wrapper_behav xil_defaultlib.Reloadable_FIR_Top_wrapper_wrapper xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-2553] file 'filepointer' is not open [/wrk/2016.4/nightly/2016_12_14_1733598/packages/customer/vivado/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd:4366]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

Please fix.

[srimaye]

Hi @dima2882 ,

Can you share your project?

Thanks,

Srimayee

[dima2882]

Hi @srimaye,

Absolutely can share the project, I just sent you a PM. Let me know if you want it another way.

I made sure all of the paths work and saved everything to a tarball. It's not very big - in testing I cut out everything unrelated to the error, so the Vivado block basically contains the FIR compiler and a wrapper, nothing else.

[jamey.hicks]

I just ran into this problem also.

[dima2882]

@jamey.hicks:

Did you run into this in Vivado 2016.4 or 2017.1? The latter was not yet out when I hit this bug...

[jamey.hicks]

I only tested it in 2016.4. If I have time, I'll try it with 2017.1 today.

[jamey.hicks]

Same behavior with 2017.1.

[bergm]

Has this issue been resolved?

I'm having a similar problem in Vivado 2017.2 using the sysgen black box with a CFR module.

Thanks

Mark

[dima2882]

Doesn't look like this has been solved, still have the same problem on 2017.2. Zero response from Xilinx on this.

[dfs342602707]

I've got the same problem here with Vivado 2017.4. Still no response from Xilinx?

mikko

[meherp]

@dfs342602707 @dima2882

Is it possible to share the project files?

[dfs342602707]

zip file attached. Go to 'simulationRun' folder and run ..\xe.bat. That produces the following error:

ERROR: [VRFC 10-2553] file 'filepointer' is not open [/wrk/2017.4/nightly/2017_12_15_2086221/packages/customer/vivado/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd:4369]

mikko

[meherp]

@dfs342602707

Do you have .slx for the design. I am getting different set of errors for the code in the zip file.

[dfs342602707]

hi,

I do not have an .slx file. I have not used Matlab or Simulink for this. Attached is a project that was used to create the filter.

mikko

[dfs342602707]

I'm still looking forward to a resolution. Xilinx, please comment further

Thanks

mikko

[dfs342602707]

"The Xilinx Community Forums is here to help! Ask questions and collaborate with Xilinx experts to get the solutions you need."

I seem to be very much alone when using the Xilinx Forums :(

[dima2882]

Yea, we all feel that way... Getting Xilinx to fix something when the forum is the only link to them just doesn't work.

Gotta be the kind of large customer they listen to :)

[kenkovaa]

Hi,

I got this example working by copying fir_compiler_1.mif file to simulationRun folder, the elaboration just did not find the coefficient file.

--Kim