UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
374 Views
Registered: ‎11-08-2017

[SystemVerilog] how to describe Look Up Table in SystemVerilog?

Hi All,

I need to declare the following Look Up Table:

.......C2 .. C1 .. C0
L0....t0 ... t1 ... t2
L1....t2 ... t1 ... t0
L2....t1 ... t0 ... t2

where t0, t1 and t2 are enum elements of the LUT.

Each element of the LUT should be referenced by (L*,C*), which are also of enum type.

Ex:
LUT(C2,L0) should refer to t0
LUT(C1,L1) should refer to t1
LUT(C0,L2) should refer to t2

So, how should I define this LUT? How should I refer the elements in the LUT?

Thank you!

0 Kudos