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Visitor
Visitor
13,281 Views
Registered: ‎09-15-2014

SystemVerilog in Vivado

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Are there plans to support any of the non-synthesisable features of SystemVerilog in the upcoming Vivado releases?

 

Will Vivado Simulator only ever support the synthesisable constructs of SV?

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Xilinx Employee
Xilinx Employee
22,656 Views
Registered: ‎09-13-2014

Hi,

 

Vivado simulator currently support all synthesizable construct. Regarding non-synthesizable contruct, can you please let us know what kind of contruct you are looking for? For support plan in vivado simulator related with non-synthesizable construct, I will request you to drop a mail to mosess@xilinx.com. He is marketing manager for vivado simulator.

 

--dhiRAj

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Xilinx Employee
Xilinx Employee
22,657 Views
Registered: ‎09-13-2014

Hi,

 

Vivado simulator currently support all synthesizable construct. Regarding non-synthesizable contruct, can you please let us know what kind of contruct you are looking for? For support plan in vivado simulator related with non-synthesizable construct, I will request you to drop a mail to mosess@xilinx.com. He is marketing manager for vivado simulator.

 

--dhiRAj

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Visitor
Visitor
13,249 Views
Registered: ‎09-15-2014

Hi,

 

I was after covergroups in particular. I get the error:

 

[XSIM 43-3980] Line 9 : The "System Verilog Covergroup" is not supported yet for simulation.

 

Thanks,

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Xilinx Employee
Xilinx Employee
13,224 Views
Registered: ‎10-24-2013
Hi,
Currently, the constructs that are supported in Vivado are given inpage 176 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug900-vivado-logic-simulation.pdf
How ever coverage support is under road map.
Thanks,Vijay
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-24-2013

Hi @tomkulaga 

Hope you got the information you are looking for.

Please close the thread by marking the solution.

 

Thanks,Vijay
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