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SystemVerilog randomizing struct throws simulator exception

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Explorer
Posts: 118
Registered: ‎03-23-2015

SystemVerilog randomizing struct throws simulator exception

Hello,

 

I am trying to write a SV class-based testbench with XSim as I have done in the past with other toolchains and I am affraid I ran into yet-another XSim limitation.

 

I have a class of which I would like to create a randomized instance. If I call randomize() on the instance everything seems to work fine, however if I use "with"  constraints in the randomiation I get an exception from the simulator with no warning or tip on how to resolve it.

 

This is a peace of code which reproduces the issue:

package MyClassPkg;

        typedef struct {
                integer element1;
                integer element2;
        } MyStructType;

        class MyClass;

                rand MyStructType bla;

        endclass : MyClass

endpackage : MyClassPkg



module MyTb ();

        initial begin
                MyClassPkg::MyClass myInstance;

                myInstance = new();
                myInstance.randomize() with {bla.element1 == 1;};

        end

endmodule : MyTb

 

When I try to simulate MyTb module I get:

 

xelab.bat -m64 --mt 8 --relax --debug typical -initfile elab.xsim.ini -log elab.log --snapshot TestSim.snapshot TestSim_lib.MyTb -L TestSim_lib -L xmp -L secureip -L unimacro_ver -L unisims_ver
INFO: [XSIM 43-3496] Using init file passed via -initfile option "elab.xsim.ini".
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.2/bin/unwrapped/win64.o/xelab.exe --mt 8 --relax --debug typical -initfile elab.xsim.ini -log elab.log --snapshot TestSim.snapshot TestSim_lib.MyTb -L TestSim_lib -L xmp -L secureip -L unimacro_ver -L unisims_ver
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module TestSim_lib.MyTb
ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. Printing stacktrace... [0] (KiUserExceptionDispatcher+0x3a) [0x7ffcfa459c8a] [1] (ISIMC::Options::parseVlogcompCommandLine+0x18a3ef) [0x7ff73a91647f] [2] [0x7ff73a5a2a49] [3] (ISIMC::VlogCompiler::transform+0xf707e) [0x7ff73a6b9dae] [4] (ISIMC::VlogCompiler::transform+0xfb9b2) [0x7ff73a6be6e2] [5] (ISIMC::VlogCompiler::transform+0x10da6e) [0x7ff73a6d079e] [6] (ISIMC::VlogCompiler::transform+0x10d929) [0x7ff73a6d0659] [7] (ISIMC::VlogCompiler::transform+0x10da8b) [0x7ff73a6d07bb] [8] (ISIMC::VlogCompiler::transform+0xf39da) [0x7ff73a6b670a] [9] (ISIMC::VlogCompiler::transform+0xef740) [0x7ff73a6b2470] [10] (ISIMC::VlogCompiler::transform+0xcbc30) [0x7ff73a68e960] [11] (ISIMC::VlogCompiler::codegen+0x446) [0x7ff73a5b6226] [12] (ISIMC::Options::parseVlogcompCommandLine+0xd798d) [0x7ff73a863a1d] [13] (ISIMC::Options::parseVlogcompCommandLine+0xd665c) [0x7ff73a8626ec] [14] (ISIMC::Options::parseVlogcompCommandLine+0xd68d8) [0x7ff73a862968] [15] (ISIMC::VhdlCompiler::saveParserDump+0x84b5e) [0x7ff73a7710ee] [16] [0x7ff73a556665] [17] [0x7ff73a565f24] [18] [0x7ff73a56493a] [19] (ISIMC::Options::parseVlogcompCommandLine+0xa71219) [0x7ff73b1fd2a9] [20] (BaseThreadInitThunk+0x14) [0x7ffcf7ba8364]

Does anybody see anything I might be doing wrong here? or should I go ahead and open a Service Request?

 

Thanks.

Xilinx Employee
Posts: 105
Registered: ‎09-25-2014

Re: SystemVerilog randomizing struct throws simulator exception

Hi @arquer,

 

This is an issue in Vivado simulator and is reported to the factory.

 

Thanks,

Srimayee