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fabiostyle
Visitor
Visitor
3,179 Views
Registered: ‎06-26-2017

SystemVerilog struct wrong behaviour

Hello to all. I'm Fabio and this is my first post. I usually try to resolve my-self the problems, but now I discovered a new one and I didn't understand it.

 

I'm using SystemVerilog over Vivado 2016.4 and I've this scenario as follow:

 

typedef struct packed {
	logic vn_packet_fifo_full;
	logic vn_packet_pending;
	logic vn_flit_valid;
	flit_t vn_flit_out;
} response_t;

response_t [1 : 0]  response_in;

assign ciao = {response_in[1].vn_packet_pending, response_in[0].vn_packet_pending} ;

But this is the result:

Cattura.PNG

 

It seems that the signal don't want to "enter" in the ciao signal (yeah, I'm from Italy).

 

Anyway, after a lot of hours, I find out two way to "resolve" the problem:

 1. using the always_comb statement like that

 

always_comb begin
    ciao[0] = response_in[0].vn_packet_pending;
    ciao[1] = response_in[1].vn_packet_pending;
end

  2. inverting struct and the array

typedef struct packed {
	logic [1:0] vn_packet_fifo_full;
	logic [1:0]vn_packet_pending;
	logic [1:0]vn_flit_valid;
	flit_t [1:0]vn_flit_out;
} response_t;

response_t   ciao;
assign ciao = {response_in.vn_packet_pending[1] , response_in.vn_packet_pending[0]} ;

Ok, now you will say: "It works, cool, have a good day". But now I want to understand why the first behaviour doesn't work, even if it is the most correct way to model my hardware.

 

So, are there some problems with the managing of struct and array in Vivado? Or are there conceptual problems?

 

If someone can explain me the cause of the problem I'll be happy for a long time and i will not waste more a lot of hour of my life.

 

Sincerely,

Fabio.

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4 Replies
muzaffer
Teacher
Teacher
3,122 Views
Registered: ‎03-31-2012

@fabiostyle you don't show the definition of ciao in the first example but assuming it is:

 

response_t [1:0] ciao;

 

then the assignment:

 

assign ciao = { ...};

is not meaningful. You are assigning a two bit long logic vector to an array of response_t. 

Show a more complete version of your code and describe what you mean to happen.

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fabiostyle
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Registered: ‎06-26-2017

Oops, sorry, my bad:

logic [1 : 0] ciao; // both cases
response_t response_in; // second case
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muzaffer
Teacher
Teacher
3,111 Views
Registered: ‎03-31-2012

@fabiostyle

 

try:

 

assign ciao = '{response_in[1].vn_packet_pending, response_in[0].vn_packet_pending} ;

 

pay attention the red ' before curly brace.

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fabiostyle
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3,094 Views
Registered: ‎06-26-2017

HI @muzaffer,

i tried your solution but nothing happened.

 

So I tried other solution and it worked! But... let me know to explain why Vivado is lazy.

 

Remember this operation?

assign ciao = {response_in[1].vn_packet_pending ,response_in[0].vn_packet_pending} ;

Good, indeed, the real operation is the following one:

typedef enum logic {
	DC_ID = 0,
	CC_ID = 1
} tile_destination_idx_t;

assign ciao  = {response_in[CC_ID].vn_packet_pending, response_in[DC_ID].vn_packet_pending} ;

I simply used a mnemonic ID in order to don't get crazy. I did't mentioned to you just to don't bother with a lot of other informations. Anyway, I want to note out that this mnemonic ID are heavily used in other parts of my code and they work correctly. So the solution with mnemonic ID works just for the ID = 0, but not for the other one.

 

So, this is basically the WORKING SOLUTION:

 

assign ciao = {response_in[1].vn_packet_pending ,response_in[DC_ID].vn_packet_pending} ;

Isn't that crazy? In all of other parts of my code the ID works fine. but just in ONE part of my code and just for ONE ID it doesn't work. That's completely impossible for me to debug this kind of problems each time.

 

Please, have you got some reasonable explanations for that? T_T

 

Kind regards,

Fabio.

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