08-21-2012 09:44 AM
When running the example design test bench with ISIM, the EMAC core component produces erroneous output (from RGMII to Local Link). RGMII data is correctly converted to 8-bit data, but then the data is presented upwards in a 16-bit vector, which contains erroneous data. Both preamble and data become corrupt. The preamble contains some unexpected zeroes, and the data seems to skip every second nibble or so (I didn't look too closely). (Note: ISIM produces the same result, regardless of 'glbl.v' being compiled and simulated with the design.) Running the same simulation with Questasim 10.1 (compiled unisim, unimacro and secureip libraries) produces correct behaviour (tested both with and without vopt flow).
08-21-2012 01:52 PM
Unfortunately, the TEMAC core does not support simulation in ISim, and ISim is not listed as one of the supported simulators in the TEMAC datasheet. Also, the Centos Lunix distribution is not supported with the ISE tools. I personally dislike the "not supported" statement, but in this case the important aspect of that is that the core will not work in ISim. Also, we have seen issues apart from ISim with unsupported linux distributions so would recommend moving to one of those for your project.
OK, I know this isn't that answer you were looking for, but hope it helps.
08-21-2012 11:55 PM
Is there a comprehensive list of ISIM limitations like this one? I've been pushing for giving ISIM a proper evaluation, and in many respects it has turned out to be quite OK, but not supporting TEMAC is a real stumbling block. Any other hard macros not supported?
A while back I saw a rather ambitious road-map with e.g. System Verilog support, but it seems to have been dropped since. Is there a plan to add support for fundamental functionality like the TEMAC, or should ISIM be seen as only suited for training and maybe low-complexity designs?
08-22-2012 04:43 AM
I can't find anything about ISIM being unsupported in the TEMAC documentation. Could you point me to the specific location for my reference?
Furthermore, I'm a tad bit curious to why I can compile and simulate the design with ISIM if this is not supported. My first impression was that this must be a bug in the ISIM simulation model.