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Visitor andreypro
Visitor
2,326 Views
Registered: ‎10-11-2017

Test bench in non module files

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Hello I am currently on Vivado 2017.2

I have a code for Zedboard and I added a testbench to Simulation soorces. My problem  is that the test bench appears as non modular file, and thus isn't recogbnised as test bench for the code

 

the entity of is following

 

entity taskb is
generic (scale: natural := 1000000000);
    port (
	clk: in std_logic;
        reset  : in std_logic;
        --  SWs_8Bits_TRI_IO  : in  STD_LOGIC_VECTOR (7 downto 0);
        BTNs_5Bits_TRI_IO : in  STD_LOGIC_VECTOR (4 downto 0);    --input  : in std_logic;
	LEDs_8Bits_TRI_IO : out STD_LOGIC_VECTOR (7 downto 0);   --output : out std_logic
	ready: out std_logic
	);
end taskb;

 

 

the test bench

entity taskb_tb is
--  Port ( );
end taskb_tb;

architecture test of taskb_tb is
	
	constant clock_cycle: time:=10 ns;
	signal up, down, left, right,center, tclk, rst: std_logic;
	signal leds: std_logic_vector (7 downto 0);
	component taskb
	generic (scale: natural := 1000000000);
    port (
        clk: in std_logic;
        reset  : in std_logic;
        --  SWs_8Bits_TRI_IO  : in  STD_LOGIC_VECTOR (7 downto 0);
        BTNs_5Bits_TRI_IO : in  STD_LOGIC_VECTOR (4 downto 0);    --input  : in std_logic;
        LEDs_8Bits_TRI_IO : out STD_LOGIC_VECTOR (7 downto 0);   --output : out std_logic
        ready: out std_logic
    );
);
		
	end component;
	begin
	DUT: taskb 
	--generic map()
	port map (clk=>tclk,
		reset=>rst,
		BTNs_5Bits_TRI_IO(0)=>left,
		BTNs_5Bits_TRI_IO(1)=>right,
		BTNs_5Bits_TRI_IO(2)=>up,
		BTNs_5Bits_TRI_IO(3)=>down,
		BTNs_5Bits_TRI_IO(4)=>center,
		LEDs_8Bits_TRI_IO=>leds);
	
	TEST_CLOCK: process
		begin
		tclk<='1';
		wait for clock_cycle/2;
		tclk<='0';
		wait for clock_cycle/2;
	end process TEST_CLOCK;

STIMULI: process

left<='0';
right<='0';
up<='0';
down<='0';
center<='0';
rst<='0';
wait for 2*clock_cycle;
assert (leds=(others=>'0')) report "Failed reset" severity error;
--other stimuli
wait;

end process STIMULI;
end test;

 

 

nmtb.png

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Xilinx Employee
Xilinx Employee
3,526 Views
Registered: ‎08-10-2015

Re: Test bench in non module files

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Hi @andreypro,

 

There are some syntax errors in the design that you have shared. There is no architecture written for taskb entity.

I have removed all the syntax errors. Design is working fine.

Please find the attached modified code.

 

 

 

Thanks,

Sunilkumar

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6 Replies
Visitor andreypro
Visitor
2,288 Views
Registered: ‎10-11-2017

Re: Test bench in non module files

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after hours of staring in the screen I manage to spot a few syntax errors. The iriginal problem was that the test bench was for some reason completely ignored and therefore Vivado didn't report errors during compilation for simulation.

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Xilinx Employee
Xilinx Employee
3,527 Views
Registered: ‎08-10-2015

Re: Test bench in non module files

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Hi @andreypro,

 

There are some syntax errors in the design that you have shared. There is no architecture written for taskb entity.

I have removed all the syntax errors. Design is working fine.

Please find the attached modified code.

 

 

 

Thanks,

Sunilkumar

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Visitor samuelcotard
Visitor
1,709 Views
Registered: ‎06-12-2015

Re: Test bench in non module files

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Hello,

 

There is a Tcl command to check syntax to help you find errors :
check_syntax.

 

Example :

check_syntax -fileset sources_1

 

Tcl command get_filesets allow you to know the exact name of the fileset you need.

 

---------------------------------------------------

LilaCo.eu - Expert in FPGA / Electronic / Embedded SW

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Adventurer
Adventurer
1,515 Views
Registered: ‎03-29-2008

Re: Test bench in non module files

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Many thanks to Samualcotard for his "check_syntax -fileset sources_1"

Why is this not a standard menu command within Vivado?

 

Nick

 

 

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Newbie ralex@ou
Newbie
1,473 Views
Registered: ‎04-02-2018

Re: Test bench in non module files

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Hello,

 

I'm a newbie in VHDL programming. Currently I'm using the Vivado 2017.4 version and trying to write a code to implement a Boolean equation. I don't see any error or warning messages for my vhdl code. However, when I try to create a file for the test bench, it becomes a non-module file. The file name for my design source is Boolean_equ1.vhd and that of my test bench is Boolean_equ1_tb.vhd. Would someone please help my understand what is going wrong here?

 

 

non-module_tb.PNG
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Moderator
Moderator
1,443 Views
Registered: ‎09-15-2016

Re: Test bench in non module files

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Hi ralex@ou,

 

Can you please create a new thread for your query rather than posting it on a close thread so that it can get better responses.

 

https://forums.xilinx.com/t5/help/faqpage/faq-category-id/posting#posting

 

Also can you please share your design to check at our end.

 

Thanks & Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
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