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alain_k
Observer
Observer
6,943 Views
Registered: ‎06-27-2014

Test pattern generator simulation

Hi

 

I tried using the test pattern generator (with a VDMA) without success, so I tried simulating it. Somehow, the TPG doesn't seem to do much and I'm not sure if it's a problem with the simultation or with the setup. But if I'm driving the inputs right, the output should work anyway, no matter what's connected to it. aclk runs on 16MHz, the rest of the setup and the simulation is in the pictures below. I ran the simulation for ~110ms, but nothing happened.

 

TPG setup

Simulation

 

Thanks

 

Alain

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bwiec
Xilinx Employee
Xilinx Employee
6,921 Views
Registered: ‎08-02-2011

Hello Alain,

It is working right, the downstream module (or your TB) is just throttling it :).

Set tready to 1.

www.xilinx.com
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alain_k
Observer
Observer
6,903 Views
Registered: ‎06-27-2014

Yes, you're right, I missed that. If I force it to a constant 1, it seems to work just fine. Nonetheless, I routed tuser, tlast and tready to an I/O. tlast and tready look ok, but tuser goes never high. That's probably the reason the VDMA gives me a SOFLate error. In the simulation, tuser works.

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bwiec
Xilinx Employee
Xilinx Employee
6,901 Views
Registered: ‎08-02-2011

Great!

 

Tuser only goes high for 1 clock cycle per frame, so it won't light an LED for very long. Have you tried inserting an ILA and triggering in tuser? Or latching tuser to the LED?

www.xilinx.com
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alain_k
Observer
Observer
6,896 Views
Registered: ‎06-27-2014

I measured it with an oscilloscope, that shouldn't be the problem. I can also measure tlast just fine and I think that's also active for just one cycle.

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