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Contributor
Contributor
1,290 Views
Registered: ‎03-04-2018

Testbench files stuck in "Non-Module Files", not added to compile

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Hi, I'm running into a problem with getting my system verilog testbench to be part of the compile process for simulation. My files get labeled under "Non-Module files". Looking at similar posts, it seems that it happens often due to syntax errors, but I have cleaned up all of the syntax errors and checked using check_syntax -fileset sim_1

 

I have a tb_top in which I invoke my testbench:

 

module tb_top;
    
    sync_test_interface _intf();
    testbench testbench_h;
    
    bit clk;
        
    CAN_router_top DUT(
        .clk(clk),
        .rstn(_intf.rst),
        .rx_in(_intf.rx_in),
        .rx_out_valid(_intf.rx_out_valid),
        .rx_out(_intf.rx_out),
        .error(_intf.error)   
    );
    
    
    initial begin
        testbench_h = new(_intf);
        testbench_h.execute();
    end
    
    //10mhz sim clock

        
    initial begin
        clk = 0;
    end
    
    always begin
        #50ns clk = ~clk;
    end
endmodule

 

I get an error when trying to run simulation:

ERROR: [VRFC 10-51] testbench is an unknown type [F:/CAN_network_router/CAN_network_router/CAN_network_router.srcs/sources_1/new/tb_top.sv:25]

And my testbench top level looks like:

class testbench;

    virtual sync_test_interface _test_signals;
    
    function new(virtual sync_test_interface _intf);
        _test_signals = _intf;
    endfunction : new
    
    task execute();
        rx_sync_test test_h;
    
        test_h = new(_test_signals);
        
        
        #1ns _test_signals.rst = 1;
        
        #100ns _test_signals.rst = 0;
        
        test_h.execute();
    endtask : execute
endclass : testbench

Can anybody advise me on why the tool isn't bringing my testbench files into compile for sim? Thanks!

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1 Solution

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Xilinx Employee
Xilinx Employee
1,586 Views
Registered: ‎08-10-2015

Re: Testbench files stuck in "Non-Module Files", not added to compile

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Hi @silverace99work,

 

You have added your class definition in file and added to project. There is no module/package definition present in the file So, Vivado is treat that file as non-module file and won't compile that file.

 

Write this class definition in the package, import in top file or cut and paste the class definition in top file will solve your problem.

 

 

 

Thanks,

Sunilkumar

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2 Replies
Xilinx Employee
Xilinx Employee
1,587 Views
Registered: ‎08-10-2015

Re: Testbench files stuck in "Non-Module Files", not added to compile

Jump to solution

Hi @silverace99work,

 

You have added your class definition in file and added to project. There is no module/package definition present in the file So, Vivado is treat that file as non-module file and won't compile that file.

 

Write this class definition in the package, import in top file or cut and paste the class definition in top file will solve your problem.

 

 

 

Thanks,

Sunilkumar

View solution in original post

Contributor
Contributor
1,241 Views
Registered: ‎03-04-2018

Re: Testbench files stuck in "Non-Module Files", not added to compile

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Ah ok. I will try that.

Since the Vivado tool was handling all my design file dependencies automatically instead of have to provide a filelist, I had assumed it would handle file dependencies for verification collateral too...strange that it does one but not the other.
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