Testbench with pipes?

[alexk@eb]

Hello,

I would like to test a VHDL module that reads input data from a programme written in C and is supposed to write response data back to the C programme. In the final implementation, the communication of the same programme will be established by a Linux Device File.

At the moment, I think about simulating the communication via two pipes, one writing from the C programme to the VHDL module and vice versa. However, the simulation stalls before a first read from pipe is executed.

Is it possible to simulate communication of the application via pipe traffic with VHDL and ModelSim? Are there better approaches for my problem?

Best regards,

Alex

[debrajr · Accepted solution]

Vivado Simulator now supports DPI - Direct Programming Interface to use your C Testbench to bind with a System Verilog code.
There is no way you can do using C and VHDL with Vivado or ISE Simulator. Not sure about Modelsim. You may post the same query in Mentor Forums and see if they have any inputs for modelsim.