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Newbie alexk@eb
Newbie
8,031 Views
Registered: ‎06-24-2015

Testbench with pipes?

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Hello,

 

I would like to test a VHDL module that reads input data from a programme written in C and is supposed to write response data back to the C programme. In the final implementation, the communication of the same programme will be established by a Linux Device File.

 

At the moment, I think about simulating the communication via two pipes, one writing from the C programme to the VHDL module and vice versa. However, the simulation stalls before a first read from pipe is executed.

Is it possible to simulate communication of the application via pipe traffic with VHDL and ModelSim? Are there better approaches for my problem?

 

Best regards,

Alex

 

 

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Moderator
Moderator
15,254 Views
Registered: ‎04-17-2011

Re: Testbench with pipes?

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Vivado Simulator now supports DPI - Direct Programming Interface to use your C Testbench to bind with a System Verilog code.
There is no way you can do using C and VHDL with Vivado or ISE Simulator. Not sure about Modelsim. You may post the same query in Mentor Forums and see if they have any inputs for modelsim.
Regards,
Debraj
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1 Reply
Moderator
Moderator
15,255 Views
Registered: ‎04-17-2011

Re: Testbench with pipes?

Jump to solution
Vivado Simulator now supports DPI - Direct Programming Interface to use your C Testbench to bind with a System Verilog code.
There is no way you can do using C and VHDL with Vivado or ISE Simulator. Not sure about Modelsim. You may post the same query in Mentor Forums and see if they have any inputs for modelsim.
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------