01-31-2018 09:40 AM
I'm trying to do a post implementation simulation. After I added a component to the simulation test bench that I'm also using in the entity under test (yes, VHDL, not Verilog), the simulation elaboration is failing with the error, "ERROR: [XSIM 43-3274] No architecture found for entity ... . The architecture may be invalidated by recompile of dependent package". The entity for which no architecture was found is the entity/architecture under test. I'm guessing that the test bench elaboration somehow invalidated the synthesis/implementation build because of the shared component. So, can/will anyone shed some light on this and how this can be remedied?
09-23-2019 10:58 AM
I'm facing the same issue.
Can't do post synthesis simulation because of a shared component that vivado recompiles, then invalidating the higher up module. What can be done?
09-23-2019 07:22 PM
If you're doing post-impl simulation from GUI, the tool will generate a post-impl simulation verilog netlist for the top level that is under test bench. The compiled files would be test bench, the .v netlist as well as glbl.v.
It sounds you add an additional submodule component to the test bench. As no file associated with the component would be compiled, you'll not be able to pass simulation.
09-24-2019 04:40 AM
Ok. That's probably it. There's a bunch of additional instances used inthe tb, which are alos used deep inside the synthesized module. Let me take look and see if I can change that.