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Visitor ysonera
Visitor
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Registered: ‎02-25-2019

The "Vhdl 2008 OPEN as Index Constraint" is not supported yet for simulation

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I encoutered the following error when doing a mixed simulation using the MPSoC verification IP and a SystemVerilog simulation testbench. The design is in VHDL. I have read some of the posts on VHDL 2008 support but it's not clear to me which part of the design is the issue here. 

TCL Console ============================================================

Completed static elaboration
ERROR: [XSIM 43-4187] File "/wrk/xhdhdnobkup3/mounicav/xsimsource/xsim_HEAD/data/vhdl/src/ieee_2008/numeric_std.vhdl" Line 73 : The "Vhdl 2008 OPEN as Index Constraint" is not supported yet for simulation.
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:19 . Memory (MB): peak = 5395.520 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '19' seconds
INFO: [USF-XSim-99] Step results log file:'C:/projects/wxr_soc/fpga/vivado/uzeg-mfr/uzeg-mfr.sim/top_sim/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/projects/wxr_soc/fpga/vivado/uzeg-mfr/uzeg-mfr.sim/top_sim/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:23 . Memory (MB): peak = 5395.520 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

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Scholar richardhead
Scholar
97 Views
Registered: ‎08-01-2012

Re: The "Vhdl 2008 OPEN as Index Constraint" is not supported yet for simulation

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If 2019.1 does not work, you'll be left with two choices:

1. Re-write the code to be Vivado friendly

2. Use a better simulator (Intel provide modelsim for free)

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Scholar richardhead
Scholar
122 Views
Registered: ‎08-01-2012

Re: The "Vhdl 2008 OPEN as Index Constraint" is not supported yet for simulation

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You dont specify what version of vivado this is with.

Xilinx is pretty much the last vendor to catch up with VHDL 2008 and is doing so very slowly and in a very annoying way where synthesis actually has better support than the simulator. 

 

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Visitor ysonera
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Registered: ‎02-25-2019

Re: The "Vhdl 2008 OPEN as Index Constraint" is not supported yet for simulation

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I'm using 2018.3.

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Scholar richardhead
Scholar
98 Views
Registered: ‎08-01-2012

Re: The "Vhdl 2008 OPEN as Index Constraint" is not supported yet for simulation

Jump to solution

If 2019.1 does not work, you'll be left with two choices:

1. Re-write the code to be Vivado friendly

2. Use a better simulator (Intel provide modelsim for free)