10-12-2018 06:08 AM
I have 2 questions. I am using vivado 2018.1 and vivado simulator. The board I am designing for is zcu111.
1) If simulation is being run, after how much time should the PLL clock outputs (clk_adc0) should show toggling?
2) Where to tell IP if it is being used in simulation or for hardware implementation? Where to set this parameter?
10-13-2018 07:13 AM
Simulation of complex blocks like those in the CMT,
Are purely functional, as the model of the actual behavior is impossible to create due to the analog nature of the block.
While running your test bench, you use the simulation models. When the bitstream gets downloaded to the device, it runs on the hardware. You use Vivado ILA to debug your design on the device. One can also use hardware co-simulation to verify your design.
10-15-2018 12:05 AM
This is not answer to my question. please read question carefully.
It says.... what is the time for RFSOC PLL to lock and output clock on clk_adc0 pin.
Also, where to tell IP that it will be used in simulation? (simulation parameter)
10-15-2018 01:13 PM
I apologize for my not understanding your question, as it makes no sense at all (to me) if what I replied is not helping,
Perhaps someone else might understand you better.
04-02-2021 08:04 AM
04-02-2021 08:24 AM
I don't remember the exact number in seconds but i remember that you have to run simulation for long (may be 200-300 msec). I remember it took my i7 with 16 gb ram around 15-20 min of time to reach where clock starts.
Regarding telling ip that it's simulation, you need to program during instructions being sent at startup. I saw the sequence of instructions going to ip from example design.
04-02-2021 12:58 PM
thanks a lot for your fast reply. Together with another of your posts I've found (https://forums.xilinx.com/t5/Versal-and-UltraScale/RFSOC-initialization-question/m-p/914822#M7973) you've made the situation clearer (I am doing as similar type of design as the one I've understood you did).