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jmcano
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Registered: ‎06-05-2013

Timing simulation not enabled

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Hi, 

 

I am using Vivado 2013.1 with a Kintex 7 KC705 Evaluation Board. I have just includes a CORDIC v.6 in my design to make a translation. I works fine in RTL design, synthesis, behavioral simulation and post-synthesis functional simulation. 

 

However, the option to perform a post-synthesis timing simulation does not appear active in Vivado. Perhaps I have missed some step. Can  you help me?

 

Thanks in advance. 

 

Jose M. Cano

jmcano@uniovi.es

 

 

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jmcano
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Registered: ‎06-05-2013

Solved. It had nothing to do with adding the IP CORDIC block. It was just that I had changed the target language options from Verilog to VHDL, and post-synthesis timing simulation was then not permitted. 

 

Excuse me for any inconvenience. 

 

jmcano

 

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jmcano
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Registered: ‎06-05-2013

Solved. It had nothing to do with adding the IP CORDIC block. It was just that I had changed the target language options from Verilog to VHDL, and post-synthesis timing simulation was then not permitted. 

 

Excuse me for any inconvenience. 

 

jmcano

 

View solution in original post

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