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Visitor ford.1441
Visitor
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Registered: ‎06-05-2018

Timing violation in PPR testbench

Hi everyone

During my post place and route testbench appears a warning timing violation:

WARNING: "C:\Xilinx\Vivado\2017.4\data/verilog/src/unisims/RAMB18E2.v" Line 2735: Timing violation in scope /tb_SP/ UUT1/i6_SP_Freq/i3_SPx4_Freq/i4_RAM0/B_RAM_G.mem_reg/TChk2735_439597 at time 3115347 ps $ setuphold (posedge  CLKBWRCLK,posedge DINADIN,(0:0:0),(0:0:0),notifier,clkbwrclk_en_p,clkbwrclk_en_p,CLKBWRCLK_delay,DINADIN_delay)

Timing report is ok, with no errors. Data are registered just before enter into the RAM block, so I can't pipeline more my design. Moreover, when data changes half cycle of clock (275 MHz) has past. I attach a screenshot of the simulation.

The clock is generated inside FPGA by a MMCM

Thanks

tb_ppr_ram.png
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