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Adventurer
Adventurer
236 Views
Registered: ‎11-18-2017

Top Module vs Component; Who has priority over generics?

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Hello.

 

I have a simple test design which uses a integer to select an output.

My top module code is like below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top_module is
    Port ( output : out std_logic_vector(9 downto 0)
          );
end top_module;

architecture Behavioral of collision is
   
    component select_comp is
        generic(selection: integer);
        port(output: out std_logic_vector(9 downto 0));
    end component;
    
begin
    cmponent1: select_comp
        generic map(selection => 9)
        port map(output => output);

end Behavioral;

And my component code is like below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity select_comp is
    generic (selection : integer := 5 );
    Port ( output : out std_logic_vector(9 downto 0) );
end select_comp;

architecture Behavioral of select_comp is
begin

process
    begin
        case selection is
            when 0 => output <= "0000000000";
            when 1 => output <= "0000000001";
            when 2 => output <= "0000000010";
            when 3 => output <= "0000000011";
            when 4 => output <= "0000000100";
            when 5 => output <= "0000000101";
            when 6 => output <= "0000000110";
            when 7 => output <= "0000000111";
            when 8 => output <= "0000001000";
            when 9 => output <= "0000001001";
            when others => output <= "0000000000";         
        end case;
        wait;   
end process;

end Behavioral;

In my component code, generic 'selection' is initialized to 5. But in my top_module code, value 9 is passed to the selection.

After simulation, the output was "0000001001"(9) so I could guess that the value which was initialized inside the component(5) is ignored or overwritten.

Is is correct?

 

Thanks for your help.

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1 Solution

Accepted Solutions
Scholar dpaul24
Scholar
223 Views
Registered: ‎08-07-2014

Re: Top Module vs Component; Who has priority over generics?

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@kimjaewon,

After simulation, the output was "0000001001"(9) so I could guess that the value which was initialized inside the component(5) is ignored or overwritten.

Is is correct?

Yes this is correct! Generic always takes precedence.

Please read a good VHDL tutorial.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
3 Replies
Scholar dpaul24
Scholar
224 Views
Registered: ‎08-07-2014

Re: Top Module vs Component; Who has priority over generics?

Jump to solution

@kimjaewon,

After simulation, the output was "0000001001"(9) so I could guess that the value which was initialized inside the component(5) is ignored or overwritten.

Is is correct?

Yes this is correct! Generic always takes precedence.

Please read a good VHDL tutorial.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
Adventurer
Adventurer
206 Views
Registered: ‎11-18-2017

Re: Top Module vs Component; Who has priority over generics?

Jump to solution
So do you mean that the generic value at the top module(9) precedence over the generic value at the component(5) in my case?
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Scholar richardhead
Scholar
167 Views
Registered: ‎08-01-2012

Re: Top Module vs Component; Who has priority over generics?

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@kimjaewon 

The component has no default value assigned. This means you technically have a missmatch.

The value assigned in the entity is just a default if no value is assigned when instantiating the entity.

 

Btw - components are not needed - they add extra burden to your code and increase compile times. It requires you to maintain 2 copies of essentially the same thing, and the compiler wont know if theres a missmatch until it gets to the mapping stage, which can be after several minutes for large designs. Using direct instatiation will cause a syntax error on a missmatch, which occurs very quick. If the source code is in VHDL, then you can use direct instantiation:

sel_inst : entity work.select_comp 
generic map (...)
port map ( ... );