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glenenglish
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Registered: ‎02-15-2014

Transition from modelsim to vivado sim

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I have a Modelsim VHDL PE seat.  not good 100% anymore due to xilinx not generating vhdl sim of many items. 

is the setup of files and simsets just a maddening mess , or am I doing it wrong ?  

I am trying to wrestle with the vivado filesets. It is like the sources management and hierarchy gets itself into a twiested, nonsense mess. It always has. Is this the experience of others ?

WHY when I add a new simulation set do all the files marked for simulation get instantly added to the new simulation set ?

for example, I might just want to run the testbench for a fifo, ONLY . nothing else. I have to go through a painful effort of disabling simulation=yes for the other simulation.  I should be able to just tag the files I want or libraries I want for this particular sim set. Otherwise WHY have different simsets at all ?

All my ip cores are compiles into my library cores_lib when I do a Modelsim simulation, and I use the compressed encrypted library output in Modelsim. That has worked fine for 15 years that way. 

I tried creating a separate project for this as outlined in UG900.  OK, so it is aware of nothiung(good), but there isnt any well documented way to tell in in files just where all the libraries are (like in Modelsim, I have a modelsim.ini file at the base of the hierarchy that tells the sim where everything is. 

When I minimise the simset for one testbench that I used to use in VHDL Modelsim, the simulator complains with stuff like this- and the : "anal0 " ip I use (a fft core) has nothing, zero zilch to do with the testbench I am trying to run . It's never mentioned and the cores_lib is never referred to in any of the simset files. never, but the simulator wants to include all of it. I want it to be seperate from the project ! IE forget the project, just give me the sim. 

Like this :'tb_anal0' is never referred ANYWHERE. WTF ???!!! why is it so keen to compile this? is this just the project mode?

why does it even want to compile the build in xilinx testbench  of the ip core ?????? why ????

:INFO: [VRFC 10-3107] analyzing entity 'tb_anal0'
ERROR: [VRFC 10-2987] 'anal0' is not compiled in library 'cores_lib' [/home/glenenglish/projects/sdr/rfip3/rfip3.gen/sources_1/ip/anal0/demo_tb/tb_anal0.vhd:208]
ERROR: [VRFC 10-3782] unit 'tb' ignored due to previous errors [/home/glenenglish/projects/sdr/rfip3/rfip3.gen/sources_1/ip/anal0/demo_tb/tb_anal0.vhd:77]
INFO: [VRFC 10-3070] VHDL file '/home/glenenglish/projects/sdr/rfip3/rfip3.gen/sources_1/ip/anal0/demo_tb/tb_anal0.vhd' ignored due to errors
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-99] Step results log file:'/home/glenenglish/projects/sdr/rfip3/rfip3.sim/tb_iqscaler/behav/xsim/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/home/glenenglish/projects/sdr/rfip3/rfip3.sim/tb_iqscaler/behav/xsim/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 10218.238 ; gain = 0.000 ; free physical = 13584 ; free virtual = 21793
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

-glen

 

 

 

 

 

 

 

 

 

 

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richardhead
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Registered: ‎08-01-2012

I highly recommend you DONT transition. keep as much as you can in modelsim. Modelsim has many many more features than XSim and far better VHDL support.

What cores are you trying to simulate? RAMs can easily be inferred and hence fifos are not much harder to create.

How about downloading the Intel webpack version of modelsim if you need a dual language licence?

https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/model-sim.html

 

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richardhead
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Registered: ‎08-01-2012

I highly recommend you DONT transition. keep as much as you can in modelsim. Modelsim has many many more features than XSim and far better VHDL support.

What cores are you trying to simulate? RAMs can easily be inferred and hence fifos are not much harder to create.

How about downloading the Intel webpack version of modelsim if you need a dual language licence?

https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/model-sim.html

 

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glenenglish
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Registered: ‎02-15-2014

Hi ...yes I agree.   and thanks for the Quartus Prime link. that'll work.

I spent today writing  FIFOs in VHDL.  Actually much time spent on the testbench. lots of tricky cases to test...

AXI RDY/VALID handshaking can vary amongst implementations. At least I will know how mine works.

cheers - glen.

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richardhead
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Registered: ‎08-01-2012

AXI ready/valid handshake is defined in the AXI standard. A transfer occurs whenever ready and valid are high at the same time. Any module that doesnt follow this handshake is NOT AXI compliant. There are no exceptions to this rule.

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glenenglish
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Registered: ‎02-15-2014

Agreed. Easy to take care of by looking at the state of READY  in the cycle after VALID was asserted. If READY was not asserted, do nothing.... otherwise bring out the next data... 

https://developer.arm.com/documentation/ihi0051/a/Interface-Signals/Transfer-signaling/Handshake-process?lang=en

AMBA 4 AXI4-Stream Protocol Specification (arm.com)

 

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richardhead
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Registered: ‎08-01-2012

For reference AXI channels can be directly connected to first word fall through FIFOs. With

wr_en <= valid;

ready_wr_side <= not full; (or almost_full if you want a packet fifo)

rd_en <= ready_rd_side;

valid_rd_side <= not empty;

 

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glenenglish
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Registered: ‎02-15-2014

ahhh very handy. thanks for that. 
today's work has been with  RAM64X1D prims..

cheers

 

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