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Visitor
Visitor
9,472 Views
Registered: ‎06-03-2013

Trouble finding Unit Under Test file during simulation

I am a new to the Xilinx ISE and iSim programs. I am working through the tutorial found attached. In the behavioral simulation chapter, on page 87 to be exact, the instructions say to expand the UUT file to be able to view the timing simulations of all of the inputs and outputs. Unfortunately, the UUT file does not apear under the test bench file as seen on the  picture on the same page. In the ISE where I created the project, the UUT file does exist, and is below the test bench file in the project design hierarchy. Does anyone know why this is happening? Thank you.

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Adventurer
Adventurer
8,740 Views
Registered: ‎08-15-2014

Please post the testbench you are using. Likely you just have the UUT named something else.

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Adventurer
Adventurer
8,739 Views
Registered: ‎08-15-2014

Also screenshots of your ISIM would be helpful to see if anything unusual is going on.

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Xilinx Employee
Xilinx Employee
8,722 Views
Registered: ‎10-24-2013

Hi,
Moving to simulation board.
Thanks,Vijay
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