06-03-2013 01:38 PM
I am a new to the Xilinx ISE and iSim programs. I am working through the tutorial found attached. In the behavioral simulation chapter, on page 87 to be exact, the instructions say to expand the UUT file to be able to view the timing simulations of all of the inputs and outputs. Unfortunately, the UUT file does not apear under the test bench file as seen on the picture on the same page. In the ISE where I created the project, the UUT file does exist, and is below the test bench file in the project design hierarchy. Does anyone know why this is happening? Thank you.
12-15-2014 07:55 PM