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wfjmueller
Explorer
Explorer
8,958 Views
Registered: ‎11-23-2009

USR_ACCESSE2 model returns 'uuuu' in simulation --> a bit user unfriendly

I use the

  set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

mechanism to have a build timestamp in the bit file and use

  USR_ACCESSE2

to read the value and make it avaialble on a diagnostic and control bus system in my designs.

 

The simulation model, at least the vhdl model USR_ACCESSE2.vhd, only returns 'uuuu...'.

Untreated that would create havoc in many simulations, the controls bus engines in general don't like undefines.

I have a catcher in my system, that writes an error message, and continues with an all '0' word.

To get even rid of this distraction I finally packed USR_ACCESSE2 into a wrapper which maps all 'u' and 'x' to '0'. Works now fine for simulation and synthesis.

 

What I wonder though is why the USR_ACCESSE2 UNISIM model is done in such an, imho, user unfriendly way. The implementation is simply

 

  architecture USR_ACCESSE2_V of USR_ACCESSE2 is
     signal CFGCLK_out : std_ulogic;
     signal DATAVALID_out : std_ulogic;
     signal DATA_out : std_logic_vector(31 downto 0);
  begin

    CFGCLK <= CFGCLK_out; 
    DATA <= DATA_out;
    DATAVALID <= DATAVALID_out;

  end USR_ACCESSE2_V;

 

so it simply returns uninitialized signals, thus (other=>'u').

 

What I'd love to have is a more simulation friendly behaviour, e.g. with a generic which allow to specify what the entiry returns in a simulation run.

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3 Replies
wfjmueller
Explorer
Explorer
8,908 Views
Registered: ‎11-23-2009

To be more precise:

  • why isn't there a SIM_.... generic which allows to setup a decent simulation behaviour.
  • that's done on several other cases, SPI_ACCESS is an example.
0 Kudos
wfjmueller
Explorer
Explorer
819 Views
Registered: ‎11-23-2009

3 years after the initial post, after 8000+ page views and a kudo, this simple module is still in the 'a bit user unfriendly' state. It is apparently too trivial to fix it. That's so sad.

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muellera
Adventurer
Adventurer
202 Views
Registered: ‎02-22-2016

The year is 2021. Vivado 2020.2 has been released. The Xilinx primitive USR_ACCESSE2 still insists that 'U' is the generally accepted output value during simulation ... kudos

0 Kudos