cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
yannik.rink
Observer
Observer
1,198 Views
Registered: ‎03-22-2019

UVM Testbench Simulation Stops 2019.2

Jump to solution

Hi,

Iam trying to run a simple Testbench example with the UVM Libary. I set all settings how it is written in the User Guide. My Simulation starts well but almost of the end my Simulation stops with following Warning:

Warning.PNG

My Simulation runs and runs but will never finish.

** Report counts by id
UVM_FATAL : 0
UVM_ERROR : 0
UVM_WARNING : 0
UVM_INFO : 4
** Report counts by severity

--- UVM Report Summary ---$finish called at time : 115 ns : File "/proj/xbuilds/SWIP/2019.2_0924_1936/installs/lin64/Vivado/2019.2/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv" Line 18699
WARNING: [Simulator 45-29] Cannot open source file /proj/xbuilds/SWIP/2019.2_0924_1936/installs/lin64/Vivado/2019.2/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv: file does not exist.

This is Output of the TCL Console

 

0 Kudos
1 Solution

Accepted Solutions
steve_farmer
Adventurer
Adventurer
886 Views
Registered: ‎06-25-2014

I've seen exactly the same fault in Ubuntu 16.04. I assume if you click cancel twice this allows the simulation to complete normally.

Also, any idea where is the location...

/proj/xbuilds/SWIP/2019.2_0924_1936/installs/lin64/Vivado/2019.2/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv

...is because I cannot see it on my computer?

 

Thanks....Steve

View solution in original post

0 Kudos
4 Replies
bandi
Moderator
Moderator
1,130 Views
Registered: ‎09-15-2016

Hi @yannik.rink 

Can you please let me know on which OS are you working upon? Please make sure that you have required read write permissions to your Vivado install directory.

Also, can you please share the UVM example test case to check at my end.

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
yannik.rink
Observer
Observer
1,067 Views
Registered: ‎03-22-2019

Hi,

iam currently working on Windows 10. My permissions of read and write of the directories and of the file seems to be correct. I attached my files from my Design and my Testbench.

 

0 Kudos
bandi
Moderator
Moderator
1,030 Views
Registered: ‎09-15-2016

Hi @yannik.rink ,

Thanks alot for sharing the files. I was able to reproduce this issue at my end and filed CR reporting it to the factory.

Can you please click on cancel twice of this pop up window as this will close the prompt.

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
steve_farmer
Adventurer
Adventurer
887 Views
Registered: ‎06-25-2014

I've seen exactly the same fault in Ubuntu 16.04. I assume if you click cancel twice this allows the simulation to complete normally.

Also, any idea where is the location...

/proj/xbuilds/SWIP/2019.2_0924_1936/installs/lin64/Vivado/2019.2/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv

...is because I cannot see it on my computer?

 

Thanks....Steve

View solution in original post

0 Kudos