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ilya1976
Participant
Participant
575 Views
Registered: ‎04-07-2014

UVM Xilinx example error

Hello,

I am trying to run UVM simulation example on Vivado 2020.2 performing step by step from

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/UVM-Universal-Verification-Methodology-Support-in-Vivado/ba-p/1070861

Unfortunately, the “adder_4_bit_tb_top.sv” file is NOT selected as the top module and after trying to launch the simulation I get errors:

 

INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Projects/sysver/project_xsim/project_xsim.srcs/sources_1/imports/Adder_4_bit/verif/env/agents/adder_4_bit_agent/adder_4_bit_agent.sv" into library xil_defaultlib
ERROR: [VRFC 10-3805] use of undefined macro 'uvm_component_utils' [D:/Projects/sysver/project_xsim/project_xsim.srcs/sources_1/imports/Adder_4_bit/verif/env/agents/adder_4_bit_agent/adder_4_bit_agent.sv:14]
ERROR: [VRFC 10-4982] syntax error near '(' [D:/Projects/sysver/project_xsim/project_xsim.srcs/sources_1/imports/Adder_4_bit/verif/env/agents/adder_4_bit_agent/adder_4_bit_agent.sv:14]
ERROR: [VRFC 10-4982] syntax error near '(' [D:/Projects/sysver/project_xsim/project_xsim.srcs/sources_1/imports/Adder_4_bit/verif/env/agents/adder_4_bit_agent/adder_4_bit_agent.sv:20]
ERROR: [VRFC 10-2989] 'adder_4_bit_driver' is not declared [D:/Projects/sysver/project_xsim/project_xsim.srcs/sources_1/imports/Adder_4_bit/verif/env/agents/adder_4_bit_agent/adder_4_bit_agent.sv:28]
ERROR: [VRFC 10-2989] 'adder_4_bit_sequencer' is not declared [D:/Projects/sysver/project_xsim/project_xsim.srcs/sources_1/imports/Adder_4_bit/verif/env/agents/adder_4_bit_agent/adder_4_bit_agent.sv:29]
ERROR: [VRFC 10-2989] 'adder_4_bit_monitor' is not declared [D:/Projects/sysver/project_xsim/project_xsim.srcs/sources_1/imports/Adder_4_bit/verif/env/agents/adder_4_bit_agent/adder_4_bit_agent.sv:30]

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1 Reply
ansarimo
Xilinx Employee
Xilinx Employee
413 Views
Registered: ‎12-04-2019

Hi @ilya1976 

As mentioned in the blog, that adder_4_bit_tb_top.sv  under simulation sources files should be selected as a top before running the simulation as can be in the snapshot below:

Capture.JPG

Mentioned error is observed if adder_4_bit_tb_top.sv is not selected as top, please try running simulation by selecting it as a top.

 

Thanks & Regards,

Ansari Hunen

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